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71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 1 of 104 a maxim integrated products brand general description the 71m6513 is a highly integrated system- on - chip so c with an mpu core, real - time clock ( rtc ) , flash, and lcd driver. our single con verter technology ? with a 21 - bit delta - sigma adc, six analog inputs, digital tem - perature compensation, precision voltage reference , and 32 - bit com putation engine (ce) supports a wide range of poly - phase metering applications with very few low - cost external components. a 3 2khz crystal time base for the entire system and internal battery - backup support for ram and rtc further reduce system cost. maximum design flexibility is supported with multiple uarts, i 2 c , a power - fail comparator, a 5v lcd charge pump, up to 22 dio pins , and an in - system programmable flash . the device is offered in high (0.1%) and standard (0.5%) accuracy versions for multifunction re si dential/commercial meter applications requiring multiple voltage/current inputs and complex lcd or dio configuratio ns. a complete array of ice and development tools, programming libraries and reference designs enable rapid development and certification of mete rs that meet most demanding worldwide electricity metering standards. features ? wh accuracy < 0.1% o ver 2 , 000:1 current r ange ? exceeds iec 62053/ansic 12.20 ? voltage r eference < 10ppm/ c ( 71m6513h ) < 4 0ppm /c ( 71m6513 ) ? six s ensor i nputs v dd r ef erenced ? auxiliary a nalog i nput for n eutral c urrent ? low j itter wh/varh p ulse o utputs ? pulse count for pulse outputs ? four - quadrant metering ? phase sequencing ? line frequency count for rtc ? digita l temperature co mpensation ? sag d etection ? independent 32 -bit compute engi ne ? 40 - 70hz line frequency range with same calibra tion ? phase c ompensation ( 7 ) ? battery backup for ram and rtc ? 22mw at 3.3v, 7.2 w b ackup ? flash memory op tion with s ecurity ? 8-b it mpu (80515) one clock cycle per i nstruction ? lcd d river ( 168 p ixels) ? high -s peed ssi serial out put ? rtc for time - of - use fu nctions ? hardware watchdog tim er ? up to 22 general - purpos e i/o p ins ? 64kb flash, 7kb ram ? two uarts for ir and amr ? 100 -p in lqfp p ackage mpu rtc timers ia va ib vb xin xout vref rx tx v1 tx rx com0..3 v2v3 v3.3a v3.3d vbat v2.5 vlcd vbias vdrv ic vc seg0..23 gnda gndd seg 24..27 dio 0..11 seg 32..41 dio 12..21 ice live live live neutral load 88.88.8888 misc power fault etc. ir amr eeprom battery comparator sense drive serial ports osc/pll converter lcd driver dio, pulse compute engine flash ram voltage ref 32 khz regulator 5v boost ct /coil power supply teridian 71m6513 3/5v lcd temp sensor 19 - 5360 ; rev 3; 9/11 single converter technology is a r egistered trademark of maxim integrated products, inc. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 2 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand table of contents features ................................................... ................................................... ...................... 1 hardware description ................................................... ................................................... .......... 9 hardware overview ................................................... ................................................... ........... 9 analog front end (afe) ................................................... ................................................... .... 9 multiplexer ................................................... ................................................... ........... 9 adc ................................................... ................................................... .................... 10 fir filter ................................................... ................................................... ............. 10 voltage reference ................................................... .................................................. 10 temperature sensor ................................................... ............................................... 11 v3 ................................................... ................................................... ....................... 11 functional description ................................................... ............................................ 11 computation engine (ce) ................................................... ................................................... .. 12 meter equations ................................................... ................................................... .. 12 pulse genera tor ................................................... ................................................... .. 13 real - time monitor ................................................... .................................................. 13 ce functional overview ................................................... ......................................... 13 80515 mpu core ................................................... ................................................... .............. 16 80515 overview ................................................... ................................................... .. 16 memory organization ................................................... ............................................. 16 special function registers (sfrs) ................................................... .......................... 18 special function registers (generic 80515 sfrs) ................................................... .. 19 special function registers specific to the 71m6513 ................................................... 22 instruction set ................................................... ................................................... ..... 23 uart ................................................... ................................................... .................. 23 timers and counters ................................................... ............................................. . 26 wd timer (software watchdog timer) ................................................... .................... 28 interrupts ................................................... ................................................... ............. 31 external interrupts ................................................... .................................................. 34 interrup t priority level structure ................................................... .............................. 35 interrupt sources and vectors ................................................... ................................. 37 on - chip resources ................................................... ................................................... ........... 39 dio ports ................................................... ................................................... ............ 39 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 3 of 104 a maxim integrated products brand physical memory ................................................... ................................................... . 41 oscillator ................................................... ................................................... ............. 42 real - time clock (r tc) ................................................... ........................................... 42 comparators (v2, v3) ................................................... ............................................. 42 lcd drivers ................................................... ................................................... ........ 43 lcd voltage boos t circuitry ................................................... .................................... 43 uart (uart0) and optical port (uart1) ................................................... ............... 44 hardware reset mechanisms ................................................... ................................. 44 re set pin (resetz) ................................................... ............................................... 44 hardware watchdog timer ................................................... ..................................... 44 crystal frequency monitor ................................................... ...................................... 44 v1 pin ................................................... ................................................... ................. 44 internal clocks and clock dividers ................................................... .......................... 45 i2c interface (eeprom) ................................................... ........................................ 45 batter y ................................................... ................................................... ................ 47 internal voltages (vbias, vbat, v2p5) ................................................... .................. 47 test ports ................................................... ................................................... ........... 47 functional descrip tion ................................................... ................................................... ........ 49 theory of operation ................................................... ................................................... .......... 49 system t iming summary ................................................... ................................................... ... 50 data flow ................................................... ................................................... ......................... 52 ce/mpu communication ................................................... ................................................... ... 52 fault, r eset, power - up ................................................... ................................................... ..... 53 battery operation ................................................... ................................................... .............. 54 power save modes ................................................... ................................................... ........... 54 chopping cir cuitry ................................................... ................................................... ............. 55 internal/external pulse generation and pulse counting ................................................... ......... 57 program security ................................................... ................................................... .............. 58 firmware int erface ................................................... ................................................... ............... 59 i/o ram map C in numerical order ................................................... ...................................... 59 sfr map (sfrs specific to teridian 80515) C in numerical order ........................................... 60 i/o ram (configuration ram) C alphabetical order ................................................... ............... 61 ce program and environment ................................................... ............................................. . 67 ce program ................................................... ................................................... ........ 67 formats ................................................... ................................................... ............... 67 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 4 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand constants ................................................... ................................................... ............ 67 environment ................................................... ................................................... ........ 67 ce calculations ................................................... ................................................... ... 68 ce ram locations ................................................... ................................................. 68 ce front end data (raw data) ................................................... ............................... 69 ce status word ................................................... ................................................... ... 69 ce transfer variables ................................................... ............................................ 70 typica l performance data ................................................... ................................................... ... 77 wh accuracy at room temperature ................................................... ..................................... 77 varh accuracy at room temperature ................................................... ................................. 77 harmonic performance ................................................... ................................................... ...... 78 application information ................................................... ................................................... ....... 79 connection of sensors (ct, resistive shunt, rogowski coil) ................................................... 79 distinction between 71m6513 and 71m6513h parts ................................................... ............. . 79 temperature compensation and mains frequency stabilization for the rtc ............................. 80 external temperature compensation ................................................... .................................... 81 temperature measurement ................................................... .................................................. 81 crys tal oscillator ................................................... ................................................... ............... 83 connecting lcds ................................................... ................................................... .............. 84 connecting i2c eeproms ................................................... ................................................... 85 connec ting 5v devices ................................................... ................................................... ..... 85 optical interface ................................................... ................................................... ................ 87 connecting v1 and reset pins ................................................... ............................................. 87 connecting the v3 pin ................................................... ................................................... ....... 88 connecting a battery ................................................... ................................................... ......... 88 flash programming ................................................... ................................................... ........... 89 mpu firmwa re library ................................................... ................................................... ....... 89 specifications ................................................... ................................................... .......................... 90 electrical specifications ................................................... ................................................... ..... 90 lo gic levels ................................................... ................................................... ... 91 vref, vbias ................................................... ................................................... ...... 93 crystal oscillat or ................................................... ........................................ 93 lcd boost ................................................... ................................................... ....... 95 lcd drivers ................................................... ................................................... .... 95 rtc ................................................... ................................................... .................... 95 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 5 of 104 a maxim integrated products brand resetz ................................................... ................................................... .............. 95 comparators ................................................... ................................................... 96 ram and flash memory ................................................... .................................. 96 flash memory timing ................................................... ...................................... 96 eeprom interface ................................................... ........................................... 96 recommended external components ................................................... ................................... 97 packaging information ................................................... ................................................... ....... 98 pinout (top view) ................................................... ................................................... 99 pin descriptions ................................................... ................................................... .. 100 i/o equivalent circuits: ................................................... ........................................... 102 ordering information ................................................... ................................................ 103 figures figure 1: ic functional block diagram .......................................................................................................................... 8 figure 2: general topology of a chopped amplifier ..................................................................................................... 10 figure 3: afe block diagram ...................................................................................................................................... 11 figure 4: samples in multiplexer cycle ....................................................................................................................... 14 figure 5: accumulation interval .................................................................................................................................. 14 figure 6: memory map .............................................................................................................................................. 16 figure 7: interrupt structure ...................................................................................................................................... 38 figure 8: dio ports block diagram ............................................................................................................................. 39 figure 9: oscillator circuit ......................................................................................................................................... 42 figure 10: lcd voltage boost circuitry ....................................................................................................................... 43 figure 11: voltage range for v1 ................................................................................................................................ 45 figure 12: voltage. current, momentary and accumulated energy ................................................................................ 49 figure 13: timing relationship between adc mux, ce, and serial transfers ................................................................ 50 figure 14: rtm output format .................................................................................................................................. 51 figure 15: ssi timing, ( ssi_fpol = ssi_rdypol = 0) ............................................................................................ 51 figure 16: ssi timing, 16 - bit field example (external device delays srdy) ................................................................ . 51 figure 17: mpu/ce data flow .................................................................................................................................... 52 figure 18: mpu/ce communication (functional) ......................................................................................................... 53 figure 19: mpu/ce communication (processing sequence) ........................................................................................ 53 figure 20: timing diagram for voltages, current and operation modes after power - up ................................................. 54 figure 21: chop polarity w/ automatic chopping ........................................................................................................ 56 figure 22: sequence with alternate multiplexer cycles ................................................................................................ 56 figure 23: sequence with alternate multiplexer cycles and controll ed chopping ........................................................... 57 figure 24: wh accuracy, 0.3a - 200a/240v ................................................................................................................ 77 figure 25: varh accuracy for 0.3a to 200a/240v performance ................................................................................... 78 figure 27: meter accuracy over harmonics at 240v, 30a ............................................................................................ 78 figure 29: resistive voltage divider (left), current transformer ( right) ......................................................................... 79 figure 30: resistive shunt ( left), rogowski coil (right) ............................................................................................... 79 figure 31: crystal frequency over temperature .......................................................................................................... 80 figure 32: crystal compensation ............................................................................................................................... 81 figure 33: error band for vref over temperature (regular - accuracy parts) ................................................................ . 83 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 6 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand figure 34: error band for vref over temperature (high - accuracy parts) ..................................................................... 83 figure 33: connecting lcds ...................................................................................................................................... 84 figure 34: lcd boost circuit ...................................................................................................................................... 85 figure 35: eeprom connection ................................................................................................................................ . 85 figure 36: interfacing rx to a 0 - 5v signal .................................................................................................................. 86 figure 37: connection for optical components ........................................................................................................... 87 figure 38: voltage divider for v1 ............................................................................................................................... 87 figure 39: external components for resetz .............................................................................................................. 88 tables table 1: inputs selected in regular and alternate multiplexer cycl es ................................................... ....... 9 table 2: ce dram locations for adc results ................................................... ...................................... 12 table 3: standard meter equations (inputs shown gray are scanned but not u sed for calculation) .............. 13 table 4: stretch memory cycle width ................................................... ................................................... 17 table 5: internal data memory map ................................................... ................................................... ... 18 table 6: special function registers locations ................................................... ...................................... 18 table 7: special function registers reset values ................................................... ................................. 20 table 8: psw register flags ................................................... ................................................... ............. 20 table 9: psw bit functions ................................................... ................................................... ................ 21 table 10: port registers ................................................... ................................................... .................... 22 table 11: special function registers ................................................... ................................................... . 23 table 12: baud rate generation ................................................... ................................................... ........ 24 table 13: uart modes ................................................... ................................................... ..................... 24 table 14: the s0con register ................................................... ................................................... ........... 24 table 15: the s1con register ................................................... ................................................... ............ 25 table 16: the s0con bit functions ................................................... ................................................... .... 25 table 17: the s1con bit functions ................................................... ................................................... .... 26 table 18: the tmod register ................................................... ................................................... ........... 26 table 19: tmod register bit description ................................................... ............................................. . 27 table 20: timers/counters mode description ................................................... ........................................ 27 table 21: the tcon register ................................................... ................................................... ............ 27 table 22: the tcon register bit functions ................................................... .......................................... 28 table 23: timer modes ................................................... ................................................... ...................... 28 table 24: the pcon register ................................................... ................................................... ........... 28 ta ble 25: the ien0 register (see also table 32) ................................................... ................................... 29 table 26: the ien0 bit functions (see also table 32) ................................................... ............................ 29 table 27: the ien1 register (see also tables 30/31) ................................................... ............................ 29 table 28: the ien1 bit functions (see also tables 30/31) ................................................... ..................... 29 table 29: the ip0 register (see also table 45) ................................................... ..................................... 30 table 30: the ip0 bit functions (see also table 45) ................................................... .............................. 30 table 31: the wdtrel register ................................................... ................................................... ....... 30 table 32: the wdtrel bit functions ................................................... ................................................... 30 table 33: the ien0 register ................................................... ................................................... .............. 32 table 34: the ien0 bit functions ................................................... ................................................... ....... 32 table 35: the ien1 register ................................................... ................................................... ............. 32 ta ble 36: the ien1 bit functions ................................................... ................................................... ...... 32 table 37: the ien2 register ................................................... ................................................... ............. 33 ta ble 38: the ien2 bit functions ................................................... ................................................... ...... 33 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71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 7 of 104 a maxim integrated products brand table 39: the tcon register ................................................... ................................................... ............ 33 table 40: the tcon bit functions ................................................... ................................................... ..... 33 table 41: the ircon register ................................................... ................................................... ........... 33 table 42: the ircon bit functions ................................................... ................................................... .... 34 table 43: external mpu interrupts ................................................... ................................................... ..... 34 table 44: control bits for external interrupts ................................................... ......................................... 35 table 45: priority level groups ................................................... ................................................... .......... 35 table 46: the ip0 register: ................................................... ................................................... ............... 36 table 47: the ip1 register: ................................................... ................................................... ............... 36 table 48: priority levels ................................................... ................................................... .................... 36 table 49: interrupt polling sequence ................................................... ................................................... . 36 table 50: interrupt vectors ................................................... ................................................... ................ 37 table 51: data registers, direction registers and internal resour ces for dio pin gro ups ........................ 39 table 52: dio_dir control bit ................................................... ................................................... ........... 40 table 53: selectable controls using the dio_dir bits ................................................... ........................... 40 table 54: mpu data memory map ................................................... ................................................... ..... 41 table 55: liquid crystal display segment table (typical) ................................................... ...................... 43 table 56: eectrl status bits ................................................... ................................................... ............ 46 ta ble 57: tmux[3:0] selections ................................................... ................................................... ........ 47 table 58: ssi pin assignment ................................................... ................................................... ........... 48 table 59: power saving measures ................................................... ................................................... ..... 54 table 60: chop_en bits ................................................... ................................................... .................... 55 table 61: frequency over temperature ................................................... ................................................ 80 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 8 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand figure 1 : ic functional block diagram ia va ib vb mux xin xout vref cktest ce 32-bit compute engine mpu (80515) ce control opt_rx opt_tx resetz v1 emulator port ce_busy optical i/f uart tx rx xfer busy ce prog ram (4kb) com0..3 lcd display driver rtc data 00-ff prog 000-7ff data 0000-ffff prog 0000-ffff mpu xram (2kb) 0000-07ff digital i/o config ram (i/o ram) 2000-20ff i/o ram ce data ram (1kb) memory share 3000-3fff 1000-13ff rtclk rtclk mux_sync ckce ckmpu v2v3 ce_run ce_load ce_en rtm_en comp_int comp_stat power fault generator and comparators lcd_en lcd_clk lcd_mode dio_gp rtc_set 4.9mhz 4.9 mhz gndd v3p3a v3p3d vbat volt reg 2.5v to logic v2p5 mpu_div sum_cycles pre_samps equ ckout_en vlcd tmuxout faultz wake vbias dmux tmux configuration parameters vdrv gnda ic temp september 19, 2005 ck_gen osc (32khz) osc_dis ck32 ck_en mck pll voltage boost lcd_bsten lcd_ibst vref vref_dis mux ctrl mux_div chop_en equ strt vc mux ckfir 4.9 mhz v3 mux_sync rtm rtm seg20..23 dio_0..3 seg28/dio8 .. seg31/dio11 gnda gndd wpulse varpulse wpulse varpulse test lcd_fs lcd_mode lcd_en gndd lcd_num dio_out dio_in lcd_num rtc_hold 0 1 2 3 4 5 6 7 8 9 a b c d e f dgnd ibias wdtr_en v2 ok v3 ok optrx analog digital pulsev/w mux_alt seg24/dio4 .. seg27/dio7 seg32/dio12 .. seg41/dio21 scl sda flash (64kb) eewrslow eerdslow v3p3a fir_len fir filter ck_10m ck_mpu reserved seg0..2, seg3/sclk, seg4/ssdata, seg5/sfr, seg7..19 eeprom interface dio_eex pll_2.5v eck_dis opt_txdis gndd ? adc converter + - vref rtclk ce_busy xfer_busy vbias v3p3 v2p5 seg6/srdy vbias vbias v3 ck32 ssi downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 9 of 104 a maxim integrated products brand hardware description hardware overview the 71m6513 single - chip polyphase meter integrates all primary functional blocks required to implement a s olid - state electricity meter. included on chip are an analog front end (afe), an 8051 - compatible microprocessor (mpu) which executes one instruction per clock cycle (80515), an independent 32 - bit digital computation engine (ce), a voltage reference, a temperature sensor, lcd drivers, ram, flash memory, a real time clock (rtc), and a variety of i/o pins. various curre nt sensor technologies are supported including current transformers (c t), resistive shunts, and rogowski ( di/dt) coils. in addition to advanced measurement functions, the real time clock function allows t he 71m6513/6513h to record time of use (tou) metering information for multi - rate applications. measurements can be displayed on either a 3v or a 5v lcd. flexible mapping of lcd display segments will facilitate integration with any lcd forma t. the design trade - off between the number of lcd segments and dio pins can be flexibly configured using memory - mapped i/o to accommodate various requirements. the 71m6513 includes several i/o peripheral functions that improve the functionality of the device and reduce the component count for most meter applications. the i/o peripherals include two uarts , digital i/o, comparator inputs, lcd display drivers, i 2 c interface and an optical/ir interface. one of the two internal uarts (uart1) is adapted to support an infrar ed led with internal drive output and sense input but it can also function as a standard uart. a block diagram of the chip is shown in figure 1 . a detailed description of various hardware blocks follows. analog front end (afe) the afe of the 71m6513 power meter ic is comprised of an input multiplexer, a delta - sigma a/d converter with a voltage reference, followed by an fir filter. a block diagram of the af e is shown in figure 3. multiplexer the input multiplexer supports eight input signals that are applied to the pins ia, va, ib, vb, ic, vc, and v3 plus the output of the internal temperature sensor. the multiplexer can be operated in two modes: ? during a normal multiplexer cycle, the signals from the six pi ns ia, va, ib, vb, ic, and vc are selected. ? during the alternate multiplexer cycle, the temperature signal (temp) a nd the additional monitor input, v3, are selected, along with the other signal sources shown in table 1 : inputs selected in regular and alternate multiplexer cycles. alternate multiplexer cycles are usually performed infrequently (every seco nd or so). va, vb, and vc are not replaced in the alternate multiplexer cycles. in some equations, currents must be delayed in allpass network s and therefore cannot be replaced in the alternate selection. missing samples due to alternate multiplexer cycles are automatically inter polated by the ce. regular multip lexer se quence mux state: alternate multiplexer se quence mux state: 0 1 2 3 4 5 0 1 2 3 4 5 ia va ib vb ic vc temp va v3 vb ic vc table 1 : inputs selected in regular and alternate multiplexer cycles in a typical application, the ia, ib, and ic inputs are connected to current transformers that sense the current on each phase of the line voltage. va, vb, and vc are typically connected to vo ltage sensors through resistor dividers. the multiplexer control circuit handles the setti ng of the multiplexer. the function of the multiplexer control circuit is governed by the i/o ram registers mux_alt (0x2005[2]), equ (0x2000[7:5]), and mux_div (0x2002[7:6]). mux_div controls the number of samples per cycle. it can request 2, 3, 4, or 6 mul tiplexer states per cycle. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 10 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand the mux_alt bit requests an alternate multiplexer cycle. the bit may be asserted on any mpu cycle and may be sub - sequently de - asserted on any cycle including the next one. a rising edge on mux_alt will cause the control circuit to wait until the next multiplexer cycle and implement a single alternate cycle. multiplexer control circuit also controls the fir filter initiation and the chopping of the adc reference voltage, vref. t he multiplexer control circuit is clocked by ck32, the 32768hz clock from the pll block, and launches each pass through the ce program. adc a single 21/22 - bit delta - sigma a/d converter digitizes the power inputs to the afe. the resolution of the adc is programmable using the i/o ram register fir_len registe r (0x2005[4]). adc resolution may be selected to be 21 bits ( fir_len =0), or 22 bits ( fir_len =1). conversion time is two cycles of ck32 with fir_len = 0 and three cycles with fir_len = 1. accuracy, timing and functional specifications in this data sheet ar e based on fir_len = 0 (two ck32 cycles). initiation of each adc conversion is controlled by the multipl exer control circuit as described previously. fir filter the finite impulse response (fir) filter is an integral part of the adc and it is optimized for use with the multiplexer. the purpose of the fir is to decimate the adc output to the desired reso lution. at the end of each adc conversion, the output data of the fir filter (raw data) is stored into the ce dram location determi ned by the multiplexer selection. the location of the raw data in the ce dram is specified in the ce program and e nvironment section. voltage reference the 71m6513/6513h includes an on - chip precision bandgap voltage reference that incorporates auto - zero techniques. the reference of the 71m6513h is trimmed in production to minimize errors caused by c omponent mismatch and drift. the result is a voltage output with a predictable temperature coefficient. the voltage reference is chopper stabilized, i.e. the polarity c an be switched by the mpu using the i/o ram register chop_en (0x2002[5:4]). the two bits in the chop_en register enable the mpu to operate the chopper circuit in regular or inverted operation, or in toggling mode. when the chopper circuit is toggled in between mult iple xer cycles, dc offsets on the measured signals will automatically be averaged out. the general topology of a chopped amplifier is given in figure 2 . figure 2 : general topology of a chopped amplifier it is assumed that an offset voltage voff appears at the positive amplifier input. with all switches, as controlled by cross in the a position, the output voltage is: voutp C voutn = g (vi np + voff C vinn) = g (vinp C vinn) + g voff g - + v inp v outp v outn v inn cross ab ab a b a b downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 11 of 104 a maxim integrated products brand with all switches set to the b position by applying the invert ed cross signal, the output voltage is: voutn C voutp = g (vinn C vinp + voff) = g (vinn C vinp) + g voff, or voutp C voutn = g (vinp C vinn) - g voff thus, when cross is toggled, e.g. after each multiplexer cycle, t he offset will alternately appear on the output as positive and negative, which results in the offset effectively being eliminated, regardless of its polarity or magnitude. the function al description section contains a chapter with a detailed descript ion on controlling the chop_en register. temperature sensor the 71m6513/6513h includes an on - chip temperature sensor implemented as a bandgap reference. it is used to determine the die tempe rature the mpu may request an alternate multiplexer cycle containing t he temperature sensor output by asserting mux_alt . the primary use of the temperature data is to determine the magnitude of compensation requi red to offset the thermal drift in the syste m (see section titled temperature compensation). the zero reference for the temperature sensor is vbias. v3 v3 is an additional analog monitor input that can be used for analog measurements, such as ne utral current. it is sampled when the multiplexer per forms an alternate multiplexer cycle. the zero reference for the v3 input is vbias. v3 is also routed into the comparator block where it is compared to vbias. comparator interrupts should be disabled when the v3 input is used for analog measurements. func tional description the afe functions as a data acquisition system, controlled by the mpu. the ma in signals (ia, va, ib, vb, ic, vc) are sampled and the adc counts obtained are stored in ce ram where the y can be accessed by the ce and, if necessary, by the mpu. alternate multiplexer cycles are initiated less frequently by the m pu to gather access to the slow signals, temperature and v3. figure 3 : afe block diagram ia va ib vb mux vref vbias ic vbias (1.5v) temp ck32 vref vref_dis mux ctrl mux_div chop_en equ vc mux v3 mux_alt v3p3a fir_len fir filter ? adc converter + - vref downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 12 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand computation engine (ce) the ce, a dedicated 32 - bit risc processor, performs the precision computations necessary to accurately measu re energy. the ce calculations and processes include: ? multiplication of each current sample with its associated voltage sample t o obtain the energy per sample (when multiplied with the const ant sample time). ? frequency - insensitive delay cancellation on all six channels (to compensate for the delay betwee n samples caused by the multiplexing scheme). ? 90 phase shifter (for var calculations). ? pulse generation. ? monitoring of the input signal freq uency (for frequency and phase information). ? monitoring of the input signal amplitude (for sag detection). ? scaling of the processed samples based on chip temperature (temperature c ompensation) and calibration coefficients. the ce program ram (ce pram) is l oaded at boot time by the mpu and then executed by the ce. each ce ins truction word is 2 bytes long. the ce program counter begins a pass through the ce code each time multiplexer state 0 begins. the code pass ends when a halt instruction is executed. for proper operation, the code pass must be completed before the multiplexer cycle ends (see system timing summary in the functio nal description section). the ce data ram (ce dram) can be accessed by the fir filter block, the rtm circuit, the ce, and the mpu. assigned time slots are reserved for fir, rtm, and mpu, respectively, such t hat memory accesses to ce_ram do not collide. holding re - gisters are used to convert 8 - bit wide mpu data to/from 32 - bit wide ce dram data, and wait states are inserted as needed, d epending on the frequency of ckmpu. table 2 shows the ce dram addresses allocated to analog inputs from the afe. address name zero reference description 0x00 ia v3p3 phase a current 0x01 va v3p3 phase a voltage 0x02 ib v3p3 phase b current 0x03 vb v3p3 phase b voltage 0x04 ic v3p3 phase c current 0x05 vc v3p3 phase c voltage 0x06 temp vbias temperature 0x07 v3 vbias v3 monitor table 2 : ce dram locations for adc results meter equations the compute engine (ce) program for industrial meter configurations impl ements the equations in table 3 . the i/o ram register equ specifies the equation to be used based on the number and arrangement of phase s used for metering. in case of single and two - phase metering, the unconnected inputs should be tied to v3p3a, the analog supply voltage. the equ selection enables the 71m6513 to calculate polyphase power measurement based on the type of ser vice used. table 3 also states the sequence of the multiplexer in the afe. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 13 of 104 a maxim integrated products brand equ watt & va r formula inputs used from mux se - quence mux state: inputs used from alternate mux sequence mux state: 0 1 2 3 4 5 0 1 2 3 4 5 0 va ia (1 element, 2w 1?) ia va ib vb ic vc temp va v3 vc ic vc 1 va(ia - ib)/2 (1 element, 3w 1?) ia va ib vb ic vc temp va ib v3 vc vc 2 va ia + vb ib (2 element, 3w 3 ?delta) ia va ib vb ic vc temp va v3 vb vc vc 3 va (ia - ib)/2 + vc ic (2 element, 4w 3? delta) ia va ib vb ic vc temp va ib v3 ic vc 4 va(ia - ib)/2 + vb(ic - ib)/2 (2 element, 4w 3? wye) ia va ib vb ic vc temp va ib v3 ic vc 5 va ia + vb ib + vc ic (3 element, 4w 3? wye) ia va ib vb ic vc temp va v3 vb ic vc table 3 : standard meter equations (inputs shown gray are scanned but not us ed for calculation) pulse generator the ce contains two pulse generators which create low jitter pu lses at a rate set by the ce dram registers apulsew * wrate and apulser * wrate if ext_pulse (a ce input variable in ce dram) is 15. this mode puts the mpu in control of puls e generation by placing values into the apulsew and apulser registers (external pulse generation). if ext_pulse is 0, apulsew is replaced with wsum_x and apulser is replaced with varsum_x . in this mode, the ce generates pulse based on its internal computation of wsum_x and var sum_x , the signed sums of energy from all three elements (internal pulse generation). the dio_pv and dio_pw bits as described in the digital i/o section can be programmed to route wpulse and var pulse to the output pins dio6 and dio7 respectively. dio6 and dio7 can be configured to generate int errupts, which can be useful for pulse counting by the mpu (see on - chip resources, dio ports section). real - time monitor the ce contains a real time monitor (rtm), which can be programmed to monitor four se lectable ce ram locations at full sample rate. the four monitored locations are serially output to the tmux out pin via the digital output multiplexer at the beginning of each ce code pass (s ee the test ports section for details) ce functional overview the adc proce sses one sample per channel per multiplexer cycle. figure 4 shows the timing of the six samples taken during one multiplexer cycle. the number of samples processed dur ing one accumulation cycle is controlled by the i/o ram registers pre_samps (0x2001[7:6]) and sum_cycles (0x2001[5:0]). the integration time for each energy output is pre_samps * sum_cycles / 2520.6, where 2520.6 is the sample rate [hz] for example, pre_sa mps = 42 and sum_cycles = 50 will establish 2100 samples per accumulation cycle. pre_samps = 100 and sum_cycles = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. a fter an accumulation cycle is completed, the xfer_busy interrupt signals to the m pu that accumulated data are available. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 14 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand figure 4 : samples in multiplexer cycle the end of each multiplexer cycle is signaled to the mpu by the ce_busy interru pt. at the end of each multiplexer cycle, status inf ormation, such as sag data and the digitized input signal, is availabl e to the mpu. figure 5 : accumulation interval figure 5 shows the accumulation interval resulting from pre_samps = 42 and sum_cycles = 50, consisting of 2100 samples of 397s each (only one phase is shown) followed by the xfer_busy interrupt. the s ampling in this example is applied to a 50hz signal. there is no correlation between the line signal frequency and the choice of pre_samps or sum_cycles ( even though when sum_cycles = 42 one set of sum_cycles happens to sample a period of 16.6ms). further more, sampling does not have to start when the line voltage crosses the zero line. delay compensation when measuring the energy of a phase (i.e., wh and varh) in a service, the voltage and curre nt for that phase must be sampled at the same instant. otherwi se, the phase difference, , introduces errors. va vb ib vc ic ia 1/2520.6hz = 397s 2/32768hz = 61.04s 13/32768hz = 397s per mux cycle a c b va vb ib vc ic ia 1/2520.6hz = 397s 2/32768hz = 61.04s 13/32768hz = 397s per mux cycle a c b xfer_busy interrupt to mpu 20ms 833ms xfer_busy interrupt to mpu 20ms 833ms downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 15 of 104 a maxim integrated products brand o delay o delay f t t t 360 360 ? ? = ? = where f is the frequency of the input signal and t delay is the sampling delay between voltage and current. in tradition al meter ics, sampling is accomplished by using two a/d converters per phase (one for voltage and the other one for current) controlled to sample simultaneously. our single - converter technology, however, ex ploits the 32 - bit signal processing capability of its ce to implement constant delay all - pass filters. these all - pass filters correct for the conversion time difference between the voltage and the corresponding current samp les that are obtained with a single multiplexed a/d converter. the constant delay all - pass filters provide a broad - band delay that is precisely matched to the differ ence in sample time between the voltage and the current of a given phase. this digital fil ter does not affect the amplitude of the signal, but provides a precisely controlled phase response. the delay compensation imp lemented in the ce aligns the voltage samples with their corresponding current samples by routing the voltage samples through the all - pass filter, thus delaying the voltage samples by , resulting in the residual phase error C . the residual phase error is negligible, and is typically less t han 1.5 milli - degrees at 100hz, thus it does not contribute to errors in the energy measur ements. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 16 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand 80515 mpu core 80515 overview the 71m6513/6513h includes an 80515 mpu (8 - bit, 8051 - compatible) that processes most instructions in one clock cycle. using a 5mhz clock results in a processing throughput of 5 mips. the 80515 architecture elim inates redundant bus states and im plements parallel execution of fetch and execution phases. normally a machine cycle is aligned with a memory fetch, there - fore, most of the 1 - byte instructions are performed in a single cycle. this leads to an 8x performance ( in average) improvement (in terms of mips ) over the intel 8051 device running at the same clock frequency . actual processor clocking speed can be adjusted to the total processing demand of the appl ication (metering calculations, amr management, memory management, lcd driver management and i/o man agement) using the i/o ram register mpu_div [2:0] . typical measurement and metering functions based on the results provided by the internal 32 - bit compute engine (ce) are available for the mpu as part of t eridian s standard library. a standard ansi c 805 15 - application programming interface library is available to help reduce design cycle. memory organization the 80515 mpu core incorporates the harvard architecture with separ ate code and data spaces. memory organization in the 80515 is similar to that of the industry standar d 8051. there are three memory areas: program memory ( flash ), external data memory (xram), physically consisting of xram, ce dram, ce pram and i/o ram, and internal data memory (internal ram). figure 6 shows the memory map (see also table 54 ). internal and external data memory: both internal and external data me mory are physically located on the 71m6513 ic. ex - ternal data memory is only external to the 80515 mpu core. 0xffff flash memory 0xffff --- 0x4000 0x3fff ce pram 0x3000 0x2fff --- 0x2100 0x20ff i/o ram 0x2000 0x1fff --- 0x1400 0x13ff ce dram 0x1000 0x0fff --- 0x0800 0x07ff xram 0xff sfrs, ram, reg. banks 0x0000 0x0000 0x00 program memory external data memory internal data memory figure 6 : memory map program memory: the 80515 can address up to 64kb of program memory space from 0x0000 to 0xffff. program memory is read when the mpu fetches instructions or performs a movc ope ration. after reset, the mpu starts program execution from location 0x00 00. the lower part of the program memory includes reset and interrupt vectors. the interrupt vectors are spaced at 8 - byte intervals, starting from 0x0003. external data memory: while the 80515 can address up to 64kb of external data memory in the space from 0x0000 to 0xffff, only the memory ranges shown in figure 6 contain physical memory. the 80515 writes into external data memory downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 17 of 104 a maxim integrated products brand when the mpu executes a movx @ri,a or movx @ dptr ,a instruction. the mpu reads external data memory by executing a movx a,@ri or movx a,@ dptr instruction (sfr usr2 provides the upper 8 bytes for the movx a ,@ri inst ruction). clock stretching: movx instructions can access fast or slow external ram and external peripherals . the three low ordered bits of the ckcon register define the stretch memory cycles. setting all the ckcon stretch bits to one allows access to very slow external ram or external peripherals. table 4 shows how the signals of the external memory interface change when stretch values are set from 0 to 7. the widths o f the signals are counted in mpu clock cycles. the post - reset state of the ckcon register, which is in bold in the table, performs the movx instructions with a stretch value equal to 1. ckcon register stretch value read signals width write signal width ckcon.2 ckcon.1 ckcon.0 memaddr memrd memaddr memwr 0 0 0 0 1 1 2 1 0 0 1 1 2 2 3 1 0 1 0 2 3 3 4 2 0 1 1 3 4 4 5 3 1 0 0 4 5 5 6 4 1 0 1 5 6 6 7 5 1 1 0 6 7 7 8 6 1 1 1 7 8 8 9 7 table 4 : stretch memory cycle width there are two types of instructions, differing in whether they provide an eight - bit or sixteen - bit indirect address to the external data ram. in the first type (movx a,@ri), the contents of r0 or r1 , in the current register bank, provide the eight lower - ordered bits of address. the eight high - ordered bits of address are specified with the usr2 sfr. this method allows the user paged access (256 pages of 256 bytes each) to the full 64kb of external data ram. in the second type of movx i nstruction (movx a,@ dptr ), th e data pointer generates a sixteen - bit address. this form is faster and more efficient when accessing very l arge data arrays (up to 64 kbytes), since no additional instructions are ne eded to set up the eight high ordered bits of address. it is possible to mix the two movx types. this provides the user with four separate data point ers, two with direct access and two with paged access to the entire 64kb of external memory range . dual data pointer: the dual data pointer accelerates the block moves of data. the standard dptr is a 16 - bit register that is used to address external memory or peripherals. in the 80515 core, the s tandard data pointer is called dptr , the second data pointer is called dptr 1. the data pointer select bit chooses the active pointer. the da ta pointer select bit is located at the lsb of the dps register ( dps .0). dptr is selected when dps .0 = 0 and dptr 1 is selected when dps .0 = 1. the user switches between pointers by toggling the lsb of the dps register. all dptr - related instructions use the currently selected dptr for any activity. the second data pointer may not be supported by certain compilers. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 18 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand internal data memory: the internal data memory provides 256 bytes (0x00 to 0xff) of data mem ory. the internal data memory address is always 1 byte wide and can be accessed by either direct or indirect addressing. the special function registers occupy the upper 128 bytes . this sfr area is available only by direct addressing. indirect addr essing accesses the upper 128 bytes of internal ram. the lower 128 bytes contain working registers and bit - addressable memory. the lower 32 bytes form four banks of eight registers (r0 - r7). two bits on the program memory status word (psw) select which bank is i n use. the next 16 bytes form a block of bit - add ressable memory space at bit addressees 0x00 - 0x7f. all of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. table 5 shows the int ernal data memory map. address direct addressing indirect addressing 0xff special function registers (sfrs) ram 0x80 0x7f byte - addressable area 0x30 0x2f bit - addressable area 0x20 0x1f register banks r0r7 0x00 table 5 : internal data memory map special function registers (sfrs) a map of the special function registers is shown in table 6. hex \ bin bit - address - able byte - addressable bin/hex x000 x001 x010 x011 x100 x101 x110 x111 f8 intbits ff f0 b f7 e8 wdi ef e0 a e7 d8 wdcon df d0 psw d7 c8 cf c0 ircon c7 b8 ien1 ip1 s0relh s1relh usr2 bf b0 flshctl pgadr b7 a8 ien0 ip0 s0rell af a0 p2 dir2 dir0 a7 98 s0con s0buf ien2 s1con s1buf s1rell eedata eectrl 9f 90 p1 dir1 dps erase 97 88 tcon tmod tl0 tl1 th0 th1 ckcon 8f 80 p0 sp dpl dph dpl1 dph1 wdtrel pcon 87 table 6 : special function registers locations only a few addresses are occupied, the others are not implemented. sfrs specific t o the 651x are shown in bold print. any read access to unimplemented addresses will return undefined data, whil e any write access will have no effect. the registers at 0x80, 0x88, 0x90, etc., are bit - addressable, all others are byte - addressable. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 19 of 104 a maxim integrated products brand special function registers (generic 80515 sfrs) table 7 shows the location of the sfrs and the value they assume at reset or power - up. name location reset value description p0 0x80 0xff port 0 sp 0x81 0x07 stack pointer dpl 0x82 0x00 data pointer low 0 dph 0x83 0x00 data pointer high 0 dpl1 0x84 0x00 data pointer low 1 dph1 0x85 0x00 data pointer high 1 wdtrel 0x86 0x00 watchdog timer reload register pcon 0x87 0x00 uart speed control tcon 0x88 0x00 timer/counter control tmod 0x89 0x00 timer mode control tl0 0x8a 0x00 timer 0, low byte tl1 0x8b 0x00 timer 1, high byte th0 0x8c 0x00 timer 0, low byte th1 0x8d 0x00 timer 1, high byte ckcon 0x8e 0x01 clock control (stretch=1) p1 0x90 0xff port 1 dps 0x92 0x00 data pointer select register s0con 0x98 0x00 serial port 0, control register s0buf 0x99 0x00 serial port 0, data buffer ien2 0x9a 0x00 interrupt enable register 2 s1con 0x9b 0x00 serial port 1, control register s1buf 0x9c 0x00 serial port 1, data buffer s1rell 0x9d 0x00 serial port 1, reload register, low byte p2 0xa0 0x00 port 2 ien0 0xa8 0x00 interrupt enable register 0 ip0 0xa9 0x00 interrupt priority register 0 s0rell 0xaa 0xd9 serial port 0, reload register, low byte p3 0xb0 0xff port 3 ien1 0xb8 0x00 interrupt enable register 1 ip1 0xb9 0x00 interrupt priority register 1 s0relh 0xba 0x03 serial port 0, reload register, high byte s1relh 0xbb 0x03 serial port 1, reload register, high byte downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 20 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand name location reset value description usr2 0xbf 0x00 user 2 port, high address byte for movx@ri ircon 0xc0 0x00 interrupt request control register psw 0xd0 0x00 program status word wdcon 0xd8 0x00 baud rate control register (only wdcon.7 bit used) a 0xe0 0x00 accumulator b 0xf0 0x00 b register table 7 : special function registers reset values accumulator (acc, a ): acc is the accumulator register. most instructions use the accumulator to hold the operand. the mnemonics for accumulator - specific instructions refer to accumulator as a, not acc. b register: the b re gister is used during multiply and divide instructions. it can also be used as a scratch - pad register to hold temporary data. program status word ( psw ): msb lsb cv ac f0 rs1 rs ov - p table 8 : psw register flags downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 21 of 104 a maxim integrated products brand bit symbol function psw.7 cv carry flag psw.6 ac auxiliary carry flag for bcd operations psw.5 f0 general purpose flag 0 available for user. not to be confused with the f0 flag in the cestatus register. psw.4 rs1 register bank select control bits. the contents of rs1 and rs0 select the working register bank: rs1/rs0 bank selected location 00 bank 0 (0x00 C 0x07) 01 bank 1 (0x08 C 0x0f) 10 bank 2 (0x10 C 0x17) 11 bank 3 (0x18 C 0x1f) psw.3 rs0 psw.2 ov overflow flag psw.1 - user defined flag psw.0 p parity flag, affected by hardware to indicate odd / even number of one bits in the accumulator, i.e. even parity. table 9 : psw bit functions stack pointer ( sp ): the stack pointer is a 1 - byte register i nitialized to 0x07 after reset. this register is incremented before push and call instructions, causing the stack to begin at location 0x08. data pointer: the data pointer ( dptr ) is 2 bytes wide. the lower part is dpl , and the highest is dph . it can be loa ded as a 2 - byte register (mov dptr ,#data16) or as two registers (e.g. mov dpl ,#data8). it is generally used to access external code or data space (e.g. movc a,@a+ dptr or movx a,@ dptr respectively). program counter: the program counter ( pc ) is 2 bytes wide initialized to 0x0000 after reset. this register is increm ented during the fetching operation code or when operating on data from program m emory. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 22 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand port registers: the i/o ports are controlled by special function registers p0, p1 , and p2 . the contents of the sfr can be observed on corresponding pins on the chip. writing a 1 to any of the ports (see table 10 ) causes the corresponding p in to be at high level (v3p3), and writing a 0 causes the corresponding pin to be held at low level (gnd ). the data direction registers dir0, dir1 , and dir2 define individual pins as input or output pins (see section on - chip resources, dio ports for deta ils). register sfr address r/w description p0 0x80 r/w register for port 0 read and write operations (pins dio0dio7) dir0 0xa2 r/w data direction register for port 0. setting a bit to 1 means that the corresponding pin is an output. p1 0x90 r/w register for port 1 read and write operations (pins dio8dio15) dir1 0x91 r/w data direction register for port 1. p2 0xa0 r/w register for port 2 read and write operations (pins dio16dio21) dir2 0xa1 r/w data direction register for port 2. table 10 : port registers all four ports on the chip are bi - directional. each of them consists of a latch (sfr p0 to p3 ), an output driver, and an input buffer, therefore the mpu can output or read data through any of these por ts. even if a dio pin is configured as an output, the state of the pin can still be read by the mpu, for example whe n counting pulses issued via dio pins that are under ce control . special function registers specific to the 71m6513 table 11 shows the location and description of the 71m6513 - specific sfrs. register alternative name sfr address r/w description erase flsh_erase 0x94 w this register is used to initiate either the flash mass erase c ycle or the flash page erase cycle. specific patterns are expected for flsh_erase in order to initiate the appropriate erase cycle (default = 0x00). 0x55 C initiate flash page erase cycle. must be proceeded by a write to flsh_pgadr @ sfr 0xb7. 0xaa C initiate flash mass erase cycle. must be proceeded by a write to flsh_meen @ sfr 0xb2 and the debug port must be enabled. any other pattern written to flsh_erase will have no effect. pgaddr flsh_pgadr 0xb7 r/w flash page erase address register containing the flash memory page address (page 0 thru 127) that will be erased during the page erase cycle (default = 0x00). must be re - written for each new page erase cycle. eedata 0x9e r/w i2c eeprom interface data register eectrl 0x9f r/w i2c eeprom interface control register. if the mpu wishes to w rite a byte of data to eeprom, it places the data in eedata and then writes the transmit code to eectrl . the write to eectrl initiates the transmit sequence. see the section i2c interface (eeprom) for a description of the command and status bits availabl e for eectrl . 0xb2 r/w bit 0 ( flsh_pwe ): program write enable: 0 C movx commands refer to xram space, normal operation (default). downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 23 of 104 a maxim integrated products brand register alternative name sfr address r/w description w r/w r 1 C movx @ dptr ,a moves a to program space ( flash ) @ dptr . this bit is automatically reset after each byte written to flash. writes to this bit are inhibited when interrupts are enabled. bit 1 ( flsh_meen ): mass erase enable: 0 C mass erase disabled (default). 1 C mass erase enabled. must be re - written for each new mass erase cycle. bit 6 ( secure ): enables security provisions that prevent external reading of flash memory and ce program ram. this bit is reset on chip reset and may only be set. attempts to write zero are ignored. bit 7 ( preboot ): indicates that the preboot sequence is active. wdi 0xe8 r/w r/w w only byte operations on the whole wdi register should be used when writing . the byte must have all bits set except the bits that are to be cleared. the multi - purpose register wdi contains the following bits: bit 0 ( ie_xfer ): xfer interrupt flag: this flag mo nitors the xfer_busy interrupt. it is set by hardware and must be cleared by the in terrupt handler bit 1 ( ie_rtc ): rtc interrupt flag: this flag mo nitors the rtc_1sec interrupt. it is set by hardware and must be cleared by the in terrupt handler bit 7 ( wd_rst ): wd timer reset: the wdt is reset when a 1 is written to this bit. intbits int0int6 0xf8 r interrupt inputs. the mpu may read these bits to see the input t o external interrupts int0, int1, up to int6. these bits do not have any memory and are primarily intended for debug use table 11 : special function registers instruction set all instructions of the generic 8051 microcontroller are supported. a compl ete list of the instruction set and of the associated op - codes is contained in the 651x software users guide (sug). uart the 71m6513 includes a uart (uart0) that can be programmed to communicate with a variety of amr modules. a second uart (uart1) is connected to the optical port, as described in the optical port description. the uart is a dedicated 2 - wire serial interface, which can communicate with an exter nal host processor at up to 38,400 bits/s ((with mpu clock = 1.2288mhz). the operation of each pin is as follows: rx : serial input data a re applied at this pin. conforming to rs - 232 standard, the bytes are input lsb first. the voltage applied at rx must not exceed 3.6v. tx : this pin is used to output the serial data. the bytes are output l sb first. the 71m6513 has several uart - related registers for the control and buffering of serial data. . a single sfr register serves as both the transmit buffer and receive buffer ( s0buf , sfr 0x99 for uart0 and s1buf , sfr 0x9c for uart1). when written by the mpu, sxbuf acts as the transmit buffer, and when read by the mpu, it acts as the receive buff er. writing data to the transmit buffer starts the transmission by the associated uart. recei ved data are available by reading from the receive buffer. both uarts can simultaneously transmit and receive data . downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 24 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand wdcon[7] selects whether timer 1 or the internal baud rate generator is use d. all uart transfers are pro grammable for parity enable, parity, 2 stop bits/1 stop bit and xon/xoff options for variable communication baud rates from 300 to 38400 bps. table 12 shows how the baud rates are calculated. table 13 shows the selectable uart operation modes. using timer 1 using internal baud rate generator serial interface 0 2 smod * f ckmpu / (384 * (256 - th1 )) 2 smod * f ckmpu /(64 * (2 10 - s0rel )) serial interface 1 n/a f ckmpu /(32 * (2 10 - s1rel )) note: s0rel and s1rel are 10 - bit values derived by combining bits from the respective timer reload registers. smod is the smod bit in the sfr pcon . th1 is the high byte of timer 1. table 12 : baud rate generation uart 0 uart 1 mode 0 n/a start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator) mode 1 start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1) start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator) mode 2 start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of f ckmpu n/a mode 3 start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator or timer 1) n/a table 13 : uart modes note: parity of serial data is available through the p flag of the accumul ator. seven - bit serial modes with parity, such as those used by the flag protocol, can be simulated by setting and reading bit 7 of 8 - bit output data. seven - bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8 - bit serial modes with parity can be simulated by setting and reading the 9 th bit, using the control bits tb80 ( s0con .3) and tb81 ( s1con .3) in the s0con and s1con sfr s for transmit and rb81 ( s1con .2) for receive operations. sm20 ( s0con .5) and sm21 ( s1con .5) can be used as handshake signals for inter - pro cessor communication in multi - processor systems. serial interface 0 control register ( s0con ). the function of the uart0 depends on the setting of the serial port control register s0con . msb lsb sm0 sm1 sm20 ren0 tb80 rb80 ti0 ri0 table 14 : the s0con register downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 25 of 104 a maxim integrated products brand serial interface 1 control register ( s1con ). the function of the serial port depends on the setting of the serial port control register s1con . msb lsb sm - sm21 ren1 tb81 rb81 ti1 ri1 table 15 : the s1con register bit symbol function s0con .7 sm0 these two bits set the uart0 mode: mode description sm0 sm1 0 n/a 0 0 1 8- bit uart 0 1 2 9- bit uart 1 0 3 9- bit uart 1 1 s0con .6 sm1 s0con .5 sm20 enables the inter - processor communication feature. s0con .4 ren0 if set, enables serial reception. cleared by software to disable reception. s0con .3 tb80 the 9 th transmitted data bit in modes 2 and 3. set or cleared by the mpu, depending on the function it performs (parity check, multip rocessor communication etc.) s0con .2 rb80 in modes 2 and 3 it is the 9 th data bit received. in m ode 1, if sm20 is 0, rb80 is the stop bit. in mode 0 this bit is not used. must be clear ed by software s0con .1 ti0 transmit interrupt flag, set by hardware after completion of a s erial transfer. must be cleared by software. s0con .0 ri0 receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software table 16 : the s0con bit functions downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 26 of 1 04 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand bit symbol function s1con .7 sm sets the baud rate for uart1 sm mode description baud rate 0 a 9- bit uart variable 1 b 8- bit uart variable s1con .5 sm21 enables the inter - processor communication feature. s1con .4 ren1 if set, enables serial reception. cleared by software to disabl e reception. s1con .3 tb81 the 9 th transmitted data bit in mode a. set or cleared by the mpu, depending on the function it performs (parity check, multiprocessor communication etc.) s1con .2 rb81 in modes 2 and 3, it is the 9 th data bit received. in mode b, if sm21 is 0, rb81 is the stop b it. must be cleared by software s1con .1 ti1 transmit interrupt flag, set by hardware after completion of a s erial transfer. must be cleared by software. s1con .0 ri1 receive interrupt flag, set by hardware after completion of a seri al reception. must be cleared by software table 17 : the s1con bit functions timers and counters the 80515 has two 16 - bit timer/counter registers: timer 0 and timer 1. these regist ers can be configured for counter or timer operations. in timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the mpu clock signal. in counter mode, the register is incremented when the falling edge is observed at the corresponding input signal t0 or t1 (t0 and t1 are the timer gating inputs derived from certain dio pins, see the dio port s chapter). since it takes 2 machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/2 of the oscillator frequency. there ar e no restrictions on the duty cycle, how ever to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle. four operating modes can be selected for timer 0 and timer 1. two special function regis ters (tmod and tcon ) are used to select the appropriate mode. timer/counter mode control register ( tmod ): msb lsb gate c/t m1 m0 gate c/t m1 m0 timer 1 timer 0 table 18 : the tmod register bits tr1 ( tcon .6) and tr0 ( tcon .4) in the tcon register (see table 21 and table 22) start their associated timers w hen set. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 27 of 104 a maxim integrated products brand bit symbol function tmod.7 tmod.3 gate if set, enables external gate control (pin int0 or int1 for count er 0 or 1, respectively). when int0 or int1 is high, and trx bit is set (see tcon register), a counter is incremented every falling edge on t0 or t1 input pin tmod.6 tmod.2 c/t selects timer or counter operation. when set to 1, a counter oper ation is performed. when cleared to 0, the corresponding register will funct ion as a timer. tmod.5 tmod.1 m1 selects the mode for timer/counter 0 or timer/counter 1, as shown in tmod description. tmod.4 tmod.0 m0 selects the mode for timer/counter 0 or timer/counter 1, as shown in tmod description. table 19 : tmod register bit description m1 m0 mode function 0 0 mode 0 13 - bit counter/timer with 5 lower bits in the tl0 or tl1 register and the remaining 8 bits in the th0 or th1 register (for timer 0 and timer 1, respectively). the 3 high order bits of tl0 and tl1 are held at zero. 0 1 mode 1 16 - bit counter/timer. 1 0 mode2 8- bit auto - reload counter/timer. the reload value is kept in th0 or th1 , while tl0 or tl1 is incremented every machine cycle. when tl(x) overflows, a value from th (x) is copied to tl (x). 1 1 mode3 if timer 1 m1 and m0 bits are set to '1', timer 1 stops. if timer 0 m1 and m0 bits are set to '1', timer 0 acts as two independent 8 - bit timer/coun ters. table 20 : timers/counters mode description note: tl0 is affected by tr0 and gate control bits, and sets tf0 flag on overflow. th0 is affected by tr1 bit, and sets tf1 flag on overflow. timer/counter control register ( tcon ) msb lsb tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 21 : the tcon register downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 28 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand bit symbol function tcon.7 tf1 the timer 1 overflow flag is set by hardware when timer 1 overfl ows. this flag can be cleared by software and is automatically cleared when an interrupt is processed. tcon.6 tr1 timer 1 run control bit. if cleared, timer 1 stops. tcon.5 tf0 timer 0 overflow flag set by hardware when timer 0 overflows. this flag can be cleared by software and is automatically cleared when an interrupt is processed. tcon.4 tr0 timer 0 run control bit. if cleared, timer 0 stops. tcon.3 ie1 interrupt 1 edge flag is set by hardware when the falling edge on ext ernal pin int1 is observed. cleared when an interrupt is processed. tcon.2 it1 interrupt 1 type control bit. selects either the falling edge or low level on input pin to cause an interrupt. tcon.1 ie0 interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is observed. cleared when an interrupt is processed. tcon.0 it0 interrupt 0 type control bit. selects either the falling edge or low level on input pin to cause interrupt. table 22 : the tcon register bit functions table 23 specifies the combinations of operation modes allowed for timer 0 and timer 1: timer 1 mode 0 mode 1 mode 2 timer 0 - mode 0 yes yes yes timer 0 - mode 1 yes yes yes timer 0 - mode 2 not allowed not allowed yes table 23 : timer modes timer/counter mode control r egister ( pcon ): msb lsb smod table 24 : the pcon register the smod bit in the pcon register doubles the baud rate when set. wd timer (software watchdog timer) the software watchdog timer is a 16 - bit counter that is incremented once every 24 or 384 clock cycles. after a reset, the watchdog timer is disabled and all registers are set to zero. the watchdog consists of a 16 - bit counter ( wdt ), a reload register ( wdtrel ), prescalers (by 2 and by 16), and control logic. once the watchdog is started, i t cannot be stopped unless the internal reset sig nal becomes active. note: it is recommended to use the hardware watchdog timer in stead of the software watchdog timer. wd timer start procedure: the wdt is started by setting the swdt flag. when the wdt register enters the state 0x7cff, an asynchronous wdts signal will become active. the signal wdts sets bit 6 in the ip0 register and requests a reset state. wdts is cleared either by the reset signal or by changing the state of the wdt. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 29 of 104 a maxim integrated products brand refreshing the wd timer: the watchdog timer must be refreshed regularly to prevent the r eset request signal from becoming active. this requirement imposes an obligation on the programmer to issue tw o instructions. the first instruction sets wdt and the second instruction se ts swdt . the maximum delay allowed between setting wdt and swdt is 12 clock cycles. if this period has expired and swdt has not been set, wdt is automatically reset, otherwise the watchdog timer is reloaded with the content of the wdtrel register and wdt i s automatically reset. since the wdt requires exact timing, firmware needs to be designed with special care in order to avoid unw anted wdt resets. teridian strongly discourages the use of the software wdt. special function registers for the wd timer interr upt enable 0 register ( ien0 ): msb lsb eal wdt et2 es0 et1 ex1 et0 ex0 table 25 : the ien0 register (see also table 32) bit symbol function ien0.6 wdt watchdog timer refresh flag. set to initiate a refresh of the watchdog timer. must be set direc tly before swdt is set to prevent an unintentional refresh of the watchdog timer. wdt is reset by hardware 12 clock cycles after it has been set. table 26 : the ien0 bit functions (see also table 32) note: the remaining bits in the ien0 register are not used for watchdog control interrupt enable 1 register ( ien1 ): msb lsb exen2 swdt ex6 ex5 ex4 ex3 ex2 table 27 : the ien1 register (see also tables 30/31) bit symbol function ien1.6 swdt watchdog timer start/refresh flag. set to activate/refresh the watchdog timer. when directly set a fter setting wdt , a watchdog timer refresh is performed. bit swdt is reset by the hardware 12 clock cycles after it has been set. table 28 : the ien1 bit functions (see also tables 30/31) note: the remaining bits in the ien1 register are not used for watchdog control downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 30 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand interrupt priority 0 register ( ip0 ): msb lsb -- wdts ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 table 29 : the ip0 register (see also table 45) bit symbol function ip0.6 wdts watchdog timer status flag. set when the watchdog timer was st arted. can be read by software. table 30 : the ip0 bit functions (see also table 45) note: the remaining bits in the ip0 register are not used for w atchdog control watchdog timer reload register ( wdtrel ): msb lsb 7 6 5 4 3 2 1 0 table 31 : the wdtrel register bit symbol function wdtrel.7 7 prescaler select bit. when set, the watchdog is clocked throu gh an additional divide - by - 16 prescaler wdtrel . 6 to wdtrel.0 6-0 seven bit reload value for the high - byte of the watchdog timer. this value is loaded to the wdt when a refresh is triggered by a consecutive sett ing of bits wdt and swdt . table 32 : the wdtrel bit functions the wdtrel register can be loaded and read at any time. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 31 of 104 a maxim integrated products brand interrupts the 80515 provides 11 interrupt sources with four priority levels. each source has its own request flag(s) located in a special function register ( tcon , ircon , and scon ). each interrupt requested by the corresponding flag can be individually enabl ed or disabled by the enable bits in sfrs ien0 , ien1 , and ien2 . external interrupts are the interrupts external to the 80515 core , i.e. signals that originate in other parts of the 71m6513/6513h, for example the ce, dio, rtc eeprom interface, comparators. interrupt overview: when an interrupt occurs, the mpu will vector to the predetermine d address as shown in table 50 . on ce interrupt service has begun, it can be interrupted only by a higher priorit y interrupt. the interrupt service is terminated by a return from instruction, "reti". when a reti instruction is perf ormed, the processor will return to the instruction that wou ld have been next when the interrupt occurred. when the interrupt condition occurs, the processor will also indicate this by se tting a flag bit. this bit is set regardless of whether the interrupt is enabled or disabled. each interrupt flag is sampled o nce per machine cycle, then samples are polled by the hardware. if the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag i s set. on the next instruction cycle, the interrupt will be acknowledged by hardware forcing an lca ll to the appropriate vector address, if the following conditions are met: ? no interrupt of equal or higher priority is already in progress. ? an instruction is currently being executed and is not completed. ? the instruction in progress is not reti or any write access to the registers ien0 , ien1 , ien2 , ip0 or ip1 . interrupt response will require a varying amount of time depending on the state of the mpu w hen the interrupt occurs. if the mpu is performing an interrupt service with equal or greater priority, the new i nterrupt will not be invoked. in other cases, the response time depends on the current instruction. the fastest possible response to a n interrupt is 7 machine cycles. this includes one machine cycle for detecting the interrupt and six cycl es to perform the lcall. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 32 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand special function registers for interrupts: interrupt enable 0 register ( ie0 ) msb lsb eal wdt es0 et1 ex1 et0 ex0 table 33 : the ien0 register bit symbol function ien0 .7 eal eal =0 C disable all interrupts ien0 .6 wdt not used for interrupt control ien0 .5 - ien0 .4 es0 es0 =0 C disable serial channel 0 interrupt ien0 .3 et1 et1 =0 C disable timer 1 overflow interrupt ien0 .2 ex1 ex1 =0 C disable external interrupt 1 ien0 .1 et0 et0 =0 C disable timer 0 overflow interrupt ien0 .0 ex0 ex0 =0 C disable external interrupt 0 table 34 : the ien0 bit functions interrupt enable 1 register ( ien1 ) msb lsb swdt ex6 ex5 ex4 ex3 ex2 table 35 : the ien1 register bit symbol function ien1.7 - ien1.6 swdt not used for interrupt control ien1.5 ex6 ex6 =0 C disable external interrupt 6 ien1.4 ex5 ex5 =0 C disable external interrupt 5 ien1.3 ex4 ex4 =0 C disable external interrupt 4 ien1.2 ex3 ex3 =0 C disable external interrupt 3 ien1.1 ex2 ex2 =0 C disable external interrupt 2 ien1.0 - table 36 : the ien1 bit functions downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 33 of 104 a maxim integrated products brand interrupt enable 2 register ( ie2 ) msb lsb - - - - - - - es1 table 37 : the ien2 register bit symbol function ien2.0 es1 es1 =0 C disable serial channel 1 interrupt table 38 : the ien2 bit functions timer/counter control register ( tcon ) msb lsb tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 39 : the tcon register bit symbol function tcon.7 tf1 timer 1 overflow flag tcon.6 tr1 not used for interrupt control tcon.5 tf0 timer 0 overflow flag tcon.4 tr0 not used for interrupt control tcon.3 ie1 external interrupt 1 flag tcon.2 it1 external interrupt 1 type control bit tcon.1 ie0 external interrupt 0 flag tcon.0 it0 external interrupt 0 type control bit table 40 : the tcon bit functions interrupt request register ( ircon ) msb lsb ex6 iex5 iex4 iex3 iex2 table 41 : the ircon register downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 34 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand bit symbol function ircon.7 - ircon.6 - ircon.5 iex6 external interrupt 6 edge flag ircon.4 iex5 external interrupt 5 edge flag ircon.3 iex4 external interrupt 4 edge flag ircon.2 iex3 external interrupt 3 edge flag ircon.1 iex2 external interrupt 2 edge flag ircon.0 - table 42 : the ircon bit functions note: only tf0 and tf1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardwar e when the service routine is called (signals t0ack and t1ack C port isr C active high when the service routine is called). external interrupts the external interrupts are connected as shown in table 43 . the po larity of interrupts 2 and 3 is programmable in the mpu. interrupts 2 and 3 should be programmed for falling sensitivity. the generic 8051 mpu literature states that interrupts 4 through 6 are defined as rising edge sensitive. thus, the hardware si gnals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in table 43 . sfr (special function register) enable bits must be set to permit any of thes e interrupts to occur. likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the mpu interrupt handler (0 through 5). xfer_busy and rtc_1sec, which are or - ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see table 44 ), and these interrupts must be cleared by the mpu software. external interrupt connection polarity f lag reset 0 digital i/o high priority see dio_rx automatic 1 digital i/o low priority see dio_rx automatic 2 comparator 2 or 3 falling automatic 3 ce_busy falling automatic 4 comparator 2 or 3 rising automatic 5 eeprom busy falling automatic 6 xfer_busy or rtc_1sec falling manual table 43 : external mpu interrupts interrupt 6 is edge -sensitive. the rtc_1sec interrupt from the rtc and the xfer_busy interrupt from the ce are com - bined using a logic or function and the result is routed into interrupt 6. therefore, both flags must be cleared at least once during initialization, and both flags must always be cleared before exiting the interrupt service routine (isr) for interrupt 6. note 1: if clearing of both flags is not per formed, then no edge can occur to trigger interrupt 6 later resulting in the isr for the xfer_busy ceasing to run. note 2: clearing both flags reliably requires some care. either flag can be set by hardware while interrupt 6 code is running on behalf of th e other interrupt. in this situation, the unprocessed interrupt can create a lockout condition similar to the one in note 1. to prevent this lockout one must always process both interru pt flags in the same service routine. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 35 of 104 a maxim integrated products brand note 3: after a reset from an in - circuit emulator, the ie_xfer flag may not be cleared because the ce may continue to run. the flags for the rtc_1sec and the xfer_busy interrupts are located in the wdi sfr (address 0xe8). enable bit description flag bit description ex0 enable external interrupt 0 ie0 external interrupt 0 flag ex1 enable external interrupt 1 ie1 external interrupt 1 flag ex2 enable external interrupt 2 iex2 external interrupt 2 flag ex3 enable external interrupt 3 iex3 external interrupt 3 flag ex4 enable external interrupt 4 iex4 external interrupt 4 flag ex5 enable external interrupt 5 iex5 external interrupt 5 flag ex6 enable external interrupt 6 iex6 external interrupt 6 flag ex_xfer enable xfer_busy interrupt ie_xfer xfer_busy interrupt flag ex_rtc enable rtc_1sec interrupt ie_rtc rtc_1sec interrupt flag table 44 : control bits for external interrupts interrupt priority level structure all interrupt sources are combined in groups, as shown in table 45 : group 0 external interrupt 0 serial channel 1 interrupt 1 timer 0 interrupt - external interrupt 2 2 external interrupt 1 - external interrupt 3 3 timer 1 interrupt - external interrupt 4 4 serial channel 0 interrupt - external interrupt 5 5 - - external interrupt 6 table 45 : priority level groups each group of interrupt sources can be programmed individually to one of four priority lev els by setting or clearing one bit in the special function register ip0 and one in ip1 . if requests of the same priority level are received simultaneously, an interna l polling sequence as per table 49 determines which request is serviced first. ien enable bits must be set to permit any of these interrupts to occur. likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the mpu interrupt handler (0 through 5). xfer_bu sy and rtc_1sec, which are or - ed together, have their own enable and flag bits in addition to the inte rrupt 6 enable and flag bits (see table 44 ), and these interrupts must be cleared by the mpu software. an overview of the interrupt structure is shown in figure 7. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 36 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand interrupt priority 0 register ( ip0 ) msb lsb -- wdts ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 table 46 : the ip0 register: note: wdts is not used for interrupt controls interrupt priority 1 register ( ip1 ) msb lsb - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 table 47 : the ip1 register: ip1.x ip0.x priority level 0 0 level0 (lowest) 0 1 level1 1 0 level2 1 1 level3 (highest) table 48 : priority levels external interrupt 0 polling sequence serial channel 1 interrupt timer 0 interrupt external interrupt 2 external interrupt 1 external interrupt 3 timer 1 interrupt external interrupt 4 serial channel 0 interrupt external interrupt 5 external interrupt 6 table 49 : interrupt polling sequence downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 37 of 104 a maxim integrated products brand interrupt sources and vectors table 50 shows the interrupts with their associated flags and vector addre sses. interrupt request flag description interrupt vector address ie0 external interrupt 0 0x0003 tf0 timer 0 interrupt 0x000b ie1 external interrupt 1 0x0013 tf1 timer 1 interrupt 0x001b ri0/ti0 serial channel 0 interrupt 0x0023 ri1/ti1 serial channel 1 interrupt 0x0083 iex2 external interrupt 2 0x004b iex3 external interrupt 3 0x0053 iex4 external interrupt 4 0x005b iex5 external interrupt 5 0x0063 iex6 external interrupt 6 0x006b table 50 : interrupt vectors downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 38 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand figure 7 : interrupt structure ie0 external interrupt flags ri1 ti1 internal interrupt flags source >=1 tf0 int2 ie1 int3 tf1 int4 ri0 ti0 >=1 int5 int6 >=1 ircon.1 i2fr ircon.2 i3fr ircon.3 ircon.4 ircon.5 ien0.7 ip1.0/ ip0.0 ip1.1/ ip0.1 ip1.2/ ip0.2 ip1.3/ ip0.3 ip1.4/ ip0.4 ip1.5/ ip0.5 interrupt control register priority assignment interrupt vector polling sequence interrupt enable logic and polarity selection dio uart1 (optical) timer 0 com par- ators com par- ators dio timer 1 ce_busy uart0 eeprom/ i2c xfer_busy rtc_1s ien0.0 ien2.0 ien0.1 ien1.1 ien0.2 ien1.2 ien0.3 ien1.3 ien0.4 ien1.4 ien1.5 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 39 of 104 a maxim integrated products brand on - chip resources dio ports the 71m6513/6513h includes up to 22 pins of general purpose digital i/o. 18 of these pins are dual function and can alternatively be used as lcd drivers. figure 8 shows a block diagram of the dio section. on reset or power - up, all dio pins are inputs until they are configured for the desired direction. the pins are configured and con trolled by the dio and dio_dir registers (sfrs) and by the five bits of the i/o register lcd_num (0x2020[4:0]). see the description for lcd_num in the i/o ram section for a table listing the available segment pins vers us dio pins, depending on the selection for lcd_num . generally, increasing the value for lcd_num will configure an increasing number of general purpose pins to be lcd segment pins, starting at the higher pin numbers . figure 8 : dio ports block diagram dio 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pin number 18 19 20 21 60 61 62 63 67 68 69 70 98 99 30 31 pin type dio multi - use multi - use data register bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 dio0=p0 (sfr 0x80) dio1=p1 (sfr 0x90) direction re gister bit -- -- -- -- 4 5 6 7 0 1 2 3 4 5 6 7 dio_dir0 (sfr 0xa2) dio_dir1 (sfr 0x91) internal re sources con figurable y y y y y y y y y y y y n n n n dio 16 17 18 19 20 21 22 23 pin number 34 16 17 64 65 66 -- -- pin type multi - use data register bit 0 1 2 3 4 5 -- -- dio2=p2 (sfr 0xa0) direction re gister bit 0 1 2 3 4 5 -- -- dio_dir2 (sfr 0xa1) internal re sources con figurable n n n n n n -- -- table 51 : data registers, direction registers and internal resources for dio pin groups com0..3 lcd display driver digital i/o lcd_en lcd_clk lcd_mode dio_gp seg20..23 dio_0..3 seg28/dio8 .. seg31/dio11 lcd_num dio_out dio_in lcd_num pulsev/w seg24/dio4 .. seg27/dio7 seg32/dio12 .. seg41/dio21 seg0..2, seg3/sclk, seg4/ssdata, seg5/sfr, seg7..19 dio_eex seg6/srdy downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 40 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand each pin declared as dio can be configured independently as an input or output with the bits of the dio_dirn registers. table 51 lists the direction registers and configurability associated with e ach group of dio pins. table 52 shows the con figuration for a dio pin through its associated bit in its dio_dir register. dio_dir bit 0 1 dio pin function input output table 52 : dio_dir control bit values read from and written into the dio ports use the data regist ers p0 , p1 and p2 . a 3 - bit configuration word, i/o ram register, dio_rx (0x2009[2:0] through 0x200e[6:4]) can be used for certain pins, when configured as dio, to individually assign an internal resource such as an interrupt or a timer control (see table 51 for dio pins available for this option). this way, dio pins can be tracked even if they are confi gured as outputs. this feature is useful for pulse counting. the control resources selectable for the dio pins a re listed in table 53 . if more than one input is connected to the same resource, the resources are combined using a logical or. dio_r value resource selected for dio pin 0 none 1 reserved 2 t0 (counter0 clock) 3 t1 (counter1 clock) 4 high priority i/o interrupt (int0 rising) 5 low priority i/o interrupt (int1 rising) 6 high priority i/o interrupt (int0 falling) 7 low priority i/o interrupt (int1 falling) table 53 : selectable controls using the dio_dir bits additionally, if dio6 and dio7 are declared outputs, they can be configure d as dedicated pulse outputs (wpulse = dio6, varpulse = dio7) using the i/o ram registers dio_pw (0x2008[2]) and dio_pv (0x2008[3]). in this case, dio6 and dio7 are under ce control. dio4 and dio5 can be configured to implement the eeprom interface by setting the i /o ram register dio_eex (0x2008[4]). downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 41 of 104 a maxim integrated products brand physical memory data bus address space is allocated to on - chip memory as shown in table 54 . address (hex) memory technology memory type typical usage wait states (at 5mhz) memory size (bytes) 0000 - ffff flash memory non - volatile program and non - volatile data 0 64kb 0000 - 07ff static ram battery - buffered mpu data ram 0 2kb 1000 - 13ff static ram volatile ce data 5 1kb 2000 - 20ff static ram volatile configuration ram (i/o ram) 0 256 3000 - 3fff static ram volatile ce program code 5 4kb table 54 : mpu data memory map flash memory: the 71m6513 includes 64kb of on - chip flash memory. the flash memory is intended to primarily contain mpu program code. in a typical application, it also contains images of the ce progra m code, ce co efficients, mpu ram, and i/o ram . on power - up, before enabling the ce, the mpu must copy these images to their respective memory locations. the i/o ram bit register flash66z defines the pulse width for accessing flash memory. to minimize supply current draw, this bit should be set to 1 . flash erasure is initiated by writing a specific data pattern to specific sfr registers in the proper sequence. these special pattern/sequence requirements prevent inadvertent erasure of the fl ash memory. the mass erase sequence is: 1. write 1 to the flsh_me en bit (sfr address 0xb2[1]. 2. write pattern 0xaa to flsh_erase (sfr address 0x94) note: the mass erase cycle can only be initiated when the ice port is enabled. the page erase sequence is: 1. write the page address to flsh_pgadr (sfr address 0xb7[7:1] 2. write pattern 0x55 to flsh_erase (sfr address 0x94) writing to flash memory: the mpu may write to the flash memory for non - volatile data storage or when implementing a boot - loader. the i/o ram register flsh_pwe (flash program write enable, sfr b2[0]) differentiates 80515 data store instructions ( movx@ dptr ,a) between flash and xram writes. before setting flsh_pwe , all interrupts need to be disabled by setting eal =1. after the write operation, flsh_pwe must be cleared. the original state of a flash byte is 0 xff (all bits are 1). over writing programmed flash cells with a different value usually re - quires that the cell is erased first. since cells cannot be erased individually , the page has to be copied to ram, followed by a page erase. after this, the page can be updated in ram and then writte n back to the flash memory. writing to flash locations will affect the corresponding xram cells, i .e. 0x2000 to 0x20ff (i/o ram), 0x0000 to 0x07ff (mpu ram), plus ce dram and ce pram. it is critical to maintain the integrity of the cells 0x20000x2007 as a minimum (where important system settings are stored) during the flash - write operation. this can be achieved by excluding the critical addresses from the write operation. mpu ram : the 71m6513 includes 2kb of static ram memory on - chip (xram), which are backed - up by the battery plus 256 - bytes of internal ram in the mpu core. the 2kb of static r am are used for data storage during normal mpu operations. ce dram: the ce dram is the data memory of the ce. the mpu can read and write the ce dram as the primary means of data communication between the two processors. ce pram: the ce pram is the program memory of the ce. the ce pram has to be loaded with ce code bef ore the ce starts operating. ce pram cannot be accessed by the mpu when the ce is running. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 42 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand oscillator the oscillator drives a standard 32.768khz watch crystal (see figure 9 ). crystals of this type are accurate and do not require a high current oscillator circuit. the oscillator in the 71m6513 power me ter ic has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capabili ty. the oscillator power dissipation is ver y low to maximize the lifetime of any battery backup device at tached to the vbat pin. figure 9 : oscillator circuit the oscillator should be placed as close as possible to the ic, a nd vias should be avoided. an external resistor a cross the crystal must not be added. real - time clock (rtc) the rtc is driven directly by the crystal oscillator. in the absence of th e 3.3v supply, the rtc is powered by the external battery (vbat pin). the rtc consists of a counter chain and output registers. the counter chain consists of seconds, minutes, hours, day of week, day of month, month, and year. the rtc is capable of processi ng leap years. each counter has its own output register. whenever the mpu reads the seconds register, all other output regi sters are automatically updated. since the rtc clock is not coherent to the mpu clock, the mpu must read the seconds regist er until two consecutive reads are the same (requires either 2 or 3 reads). at this point, all rtc output registers wi ll have the correct time. regardless of the mpu clock speed, rtc reads require one wait state. the rtc interrupt must be enabled using the i/o ram register ex_rtc (address 0x2002[1]). rtc time is set by writing to the i/o ram registers rtc_sec , rtc_min , through rtc_yr. each byte written to rtc must be delayed at least 3 ck32 cycles from any previous byte written to rtc. two time correction bits, the i/o ram registers rtc_dec_sec (0x201c[1]) and rtc_inc_sec (0x201c[0]) are provided to adjust the rtc time. a pulse on one of these bits causes the time to be decremented or incremented by an additional second at the next update of the rtc_sec register. thus, if the crystal temperature coefficient is know n, the mpu firmware can integrate temperature and correct the rtc time as necessary as discussed in temperature compensation. comparators (v2, v3) the 71m6513/6513h includes two programmable comparators that are connected to the v2 and v3 pins . the i/o ram register comp_int (0x2003[4:3]) allows the user to determine if comparat ors 2 and 3 will trigger an interrupt to the mpu. the output of each comparator is available in the compstat register. vbias is used as the threshold, and built - in hysteresis prevents each com parator from repeatedly responding to low - amplitude noise. comp arators 2 and 3 can be used for early warning of power faults, or for monitoring of battery or other dc voltages. if they are both selected to interrupt the mpu, their outputs will be xore d together. the voltage at v3 is also available to the adc in the afe, but the comparator should not be used when v3 is used for analog measurements. comparator 1 is part of the power fault circuitry (see section v1 pin) and cannot be programmed. crystal xout xin 71m651x downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 43 of 104 a maxim integrated products brand lcd drivers the 71m6513 contains 24 dedicated lcd segment drivers and 18 mul ti - purpose pins which may be configured as additional lcd segment drivers (see i/o ram register lcd_num ). the 71m6513/6513h is capable of driving between 96 to 168 pixels of lcd display with 25% duty cycle. at seven segments per digit, the lcd can be de signed for 13 to 24 digits for display. since each pixel is addressed individually, the lcd display can be a combination of al phanumeric digits and enunciator symbols. the information to be displayed is written into the lower four bits o f i/o ram registers lc d_seg0 through lcd_seg41 . bit 0 corresponds to the segment selected when com0 pin is act ive while bit 1 is allocated to com1. the lcd driver circuitry is grouped into 4 common outputs (com0 to com3) and up to 42 se gment outputs (see table 55 ). the typical lcd map is shown below. seg0 seg1 seg2 seg3 seg27 seg41 com0 p0 p4 p8 p12 ... p108 ... p164 com1 p1 p5 p9 p13 p109 ... p165 com2 p2 p6 p10 p14 ... p110 ... p166 com3 p3 p7 p11 p15 ... p111 ... p167 table 55 : liquid crystal display segment table (typical) note: p0, p1, represent the pixel/segment numbers on the lcd. a charge pump suitable for driving vlcd is included on - chip. this circuit creates 5v from the 3.3v supply. a contrast dac is provided that permits the lcd full - scale voltage to be adjusted between vlcd and 70% of vlcd. the lcd_num register defines the numb er of dual purpose pins used for lcd segment interface. lcd voltage boost circuitry a voltage boost circuit may be used to generate 5v from the 3.3v s upply to support low - power 5v devices, such as lcds. figure 10 shows a block diagram of the voltage boost circuitry including the voltage regulat ors for v2p5 and v2p5nv. when activated using the i/o ram register lcd_bsten (0x2020[7]), the boost circuitry provides an ac voltage at the vdrv output pin (see the applications section for details). figure 10 : lcd voltage boost circuitry gndd v3p3d vbat volt reg 0.1v v2p5 vlcd vdrv voltage boost lcd_bsten lcd_ibst gndd gndd gndd v2p5 v3p3d v2p5nv downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 44 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand uart (uart0) and optical port (uart1) the 71m6513/6513h includes an interface to implement an ir or optical port. the pin opt_tx is designed to directly drive an external led for transmitting data on an optical link (low - active). the pin opt_rx, also low -active, is designed to sense the input from an external photo detector used as the receiver for th e optical link. thes e two pins are connected to a dedicated uart port. opt_tx can be tristated if it is desired to multiplex another i/ o pin to the opt_tx output. the control bit for th e opt_tx output is the i/o ram register opt_txdis (0x2008[5]). hardware reset mechanisms se veral conditions will cause a hardware reset of the 71m6513/6513h: ? voltage at the resetz pin low ? voltage at the e_rst pin low ? voltage at the v1 pin below reset threshold (vbias) ? the crystal frequency monitor detected a crystal malfunction ? hardware watchdog timer reset pin (resetz) when the resetz pin is pulled low (or when v1 < vbias), all di gital activity in the chip stops while analog circuits are sti l l active. the oscillator and rtc module continue to run. additionally , all i/o ram bits are cleared. hard ware watchdog timer in addition to the basic software watchdog timer included in the 80515 mpu, an i n de pendent, robust, fixed - duration, hardware watchdog timer (wdt) is included in the 71m6513/6513h. this timer will reset the mpu i f it is not refreshed periodically, and can be used to recover the mpu in situations where program control i s lost. the watchdog timer uses the rtc crystal oscillator as its time base and require s a reset under mpu program control at least every 1.5 seconds. when the wdt overfl ow occurs, the mpu is momentarily reset as if resetz were pulled low f or half of a crystal oscillator cycle. thus, after 4100 cycles of ck32 (3 2768hz clock) , the mpu program will be launched from address 00. an i/o ram register status bit, wd_ovf (0x2002[ 2]), is set when wdt overflow occurs . this bit is powered by the vbat pin and can be read by the mpu to determine if the part is initializing after a wdt overflow ev ent or after a power up. after reading this bit, mpu firmware must clear wd_ovf . the wd_ovf bit is also cleared by the resetz pin. the watchdog timer also includes an oscillator check. if the cry stal oscillator stops or slows down, wd_ovf is set and a system reset will be performed when the crystal oscillator r esumes. there is no internal digit al state that deactivates the wdt. for debug purposes, however, the wdt can be disab led by tying the v1 pin to v3p3 (see figure 11 and wd disable threshold [v1 - v3p3a] in the comparator section of the electrical specifications). of course, this also deactivates the power fault detecti on implemented with v1. since there is no way in fir m- ware to disable the crystal oscillator or the wdt, it is guara nteed that whatever st ate the mpu might find itself in, it will be reset to a known state upon watchdog timer overflow. in normal operation, the wdt is reset by periodically writing a one to the wdt_rst bit. the watchdog timer is also reset when wake=0 and, during development, when a 0x14 command is received from the ice port. crystal frequency monitor the hardware watchdog timer also includes an oscillator check. if the crystal os cillator stops or slows down, the i/o ram register wd_ovf is set and a system reset will be performed when the crystal os cillator resumes. v1 pin the comparator at the v1 pin controls the state of the digital c ircuitry on the chip. when v1 < vbias (or when the res e tz pin is pulled low), all digital activity in the chip stops while analog circuits inclu ding the oscillator and rtc module are still active. additionally, when v1 < vbias, all i/o ram bits are cleared. as long as v1 is g reater than vbias, the internal 2.5v regulator will continue to provide power to the digital section. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 45 of 104 a maxim integrated products brand figure 11 : voltage range for v1 internal clocks and clock dividers all internal clocks are based on the watch crystal frequency (ck32 = 32,768hz) app lied to the xin and xout pins. the pll multiplies this frequency by 150 to 4.9152mhz. this frequency is supplied to the adc, the fir filter (c kfir), the clock test output pin (cktest), the ce dram and the clock generator. the clock generator provide s two clocks, one for the mpu (ckmpu) and one for the ce (ckce). the mpu clock frequency is determined by the i/o ram register mpu_div (0x2004[2:0]) and can be ce*2 - mpu_div hz where mpu_div varies from 0 to 7 ( mpu_div is 0 on power - up). this makes the mpu clock scalable from 4.9152mhz down to 38.4khz. the circuit also g e nerates a 2x mpu clock for use by the emulator. this clock is not generated when the i/o ram register eck_dis (0x2005[5]) is asserted by the mpu. i2c interface (eeprom) a dedicated 2 - pin serial interface implements an i2c driver that can be used to commu nicate with external eeprom devices. the interface can be multiplexed onto the dio pins dio4 (sck) and di o5 (sda) by setting the i/o ram register dio_eex (0x2008[4]). the mpu communicates with the interface through two sfr registers: eedata (0x9e) and eectrl (0x9f). if the mpu wishes to write a byte of data to eeprom, it places the data i n eedata and then writes the transmit code to eectrl . the write to eectrl initiates the transmit sequence. by observing the busy bit in eectrl the mpu can determine when the transmit operation is finished (i.e. when the busy bit transitions from 1 to 0). int5 is also asserted when busy falls. the mpu can then check the rx_ack bit to see if the eeprom acknowledged the transmission. a byte is read by writing the receive c ommand to eectrl and waiting for busy to fall. upon completion, the received data will appear in eedata . the serial transmit and receive clock is 78khz during each transmission, and sc l is held in a high state until the next transmission. the bits in eectr l are shown in table 56 . the eeprom interface can also be operated by controlling the dio4 and di o5 pins directly. however, controlling dio4 and dio5 directly is discouraged, because it may tie up the mpu to the point where it may become too busy to process interrupts . v3p3 v3p3 - 400mv v3p3-10mv vbias 0v battery or reset mode normal operation, wdt enabled wdt dis- abled v1 when (v1 < vbias) the battery is enabled downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 46 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand note: clock stretchi ng and multi - master operation are not supported for the i 2 c interface. status bit name read/ write reset state polarity descri ption 7 error r 0 positive 1 when an illegal command is received. 6 busy r 0 positive 1 when serial data bus is busy. 5 rx_ack r 1 negative 0 indicates that the eeprom sent an ack bit. 4 tx_ack r 1 negative 0 indicates when an ack bit has been sent to the eeprom 3-0 cmd[3:0] w 0 positive, see cmd table cmd operation 0 no - op. applying the no - op command will stop t he i2c clock (sck, dio4). failure to issue the no - op command will keep the sck signal toggling. 2 receive a byte from eeprom and send ack. 3 transmit a byte to eeprom. 5 issue a stop sequence. 6 receive the last byte from eeprom and do not send ack. 9 issue a start sequence. others no operation, set the error bit. table 56 : eectrl status bits downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 47 of 104 a maxim integrated products brand battery the vbat pin provides an input for an external battery that can be used to support the crystal oscillator, rtc, the wd_ovf bit and xram in the absence of the main power supply. if the battery i s not used, the vbat pin should be connected to v3p3. internal voltages (vbias, vbat, v2p5) the 71m6513 requires two supply voltages, v3p3a, for the analog section, and v3p3d, for the dig ital section. both voltages can be tied together outside the chip. the internal supply voltage v 2p5 is generated by a regulator from the 3.3v supplies. the battery voltage, vbat, is required when crystal oscillator, rtc and xra m are required to keep operating while v3p3d is re moved (battery mode). vbat, usually supplied by an external battery, powers crystal oscillator, rtc and xram (and the wd_ovf bit). vbias (1.5v) is generated internally and used for the comparators v1 , v2 and v3. test ports tmuxout pin: one out of 16 digital or 4 analog signals can be selected to be output on the tmuxout pin. the funct ion of the multiplexer is con trolled with the i/o ram register tmux (0x2000[3:0]), as shown in table 57 . tmux [3:0] mode function 0 analog dgnd 1 analog ibias 2 analog pll_2.5v 3 analog vbias 4 digital rtm (real time output from ce) 5 digital wdtr_en (comparator 1 output and v1lt3) 6 digital v2_ok (comparator 2 output) 7 digital v3_ok (comparator 3 output) 8 digital rxd (from optical interface) 9 digital mux_sync a digital ck_10m b digital ck_mpu c -- reserved for production test d digital rtclk e digital ce_busy f digital xfer_busy table 57 : tmux [3:0] selections emulator port: the emulator port, consisting of the pins e_rst, e_tclk and e_rxtx provides control of the mpu through an external in - circuit emulator. the e_tbus[3:0] pins, together with the e_isync/brkrq add trace capability to the emulator. the emulator port is compatible with the adm51 emulators manufactured by signum systems. the signals of the emulator port have weak pull - ups. adding 1k ? pull - up resistors on the pcb is recommend ed. real - time monitor: the rtm output of the ce is available as one of the digital multiplexer options. rtm data is r ead from the ce dram locations specified by i/o ram registers rtm0 , rtm1 , rtm2 , and rtm3 after the rise of mux_sync. the rtm can be enabled and disabled with i/o ram register rtm_en . the rtm output is clocked by cktest. each rtm word is clocked downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 48 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand out in 35 cycles and contains a leading flag bit. figure 13 in the system timing section illustrates the rtm output form at. rtm is low when not in use. ssi interface: a high - speed serial interface with handshake capability is available to s end a contiguous block of ce data to an external data logger or dsp. the block of data, configurable as to location and size, is sent starting 1 cycle of 32khz befor e each ce code pass begins. if the block of data is big enough that transmi ssion has not completed when the code pass begins, it will complete during the ce code pass with no timing impact to the ce or the seri al data. in this case, care must be taken that the transmitted data is not modified unexpectedly by the ce. the ssi interface is enabled by the ssi_en bit and consists of sclk, ssdata, and sfr as outputs and, optionally, srdy as input. the interface is compatible with 16bit and 32bit processors. the operation of each pin is as follows: sclk is the serial clock. the clock can be 5mhz or 10mhz, as specified by the ssi_10m bit. the ssi_ckgate bit controls whether sclk runs continuously or is gated off when no ssi activity i s occurring. if sclk is gated, it will begin 3 cycles be fore sfr rises and will persist 3 cycles after the last data bit i s output. the pins used for the ssi are multiplexed with the lcd segment outputs, as shown in table 58 . thus, the lcd should be disabled when the ssi is in use. ssi signal lcd segment output pin sclk seg3 ssdata seg4 sfr seg5 srdy seg6 table 58 : ssi pin assignment srdy is an optional handshake input that indicates that the dsp or data - logging device is ready to receive data. srdy must be true (the polarity of srdy is selectable with ssi_fpol ) to enable sfr to rise and initiate the transfer of the next field. it is expected that srdy changes state on the rising edges of sclk. if srd y is not true when the ssi port is ready to transmit the next field, transmission will be delayed until it is. srdy is ignored exce pt at the beginning of a field transmission. if srdy is not enabled (by ssi_rdyen ), the ssi port will behave as if srdy is always true. ssdata is the serial output data. ssdata changes on the rising edge of sclk and outputs the co ntents of a block of ce ram words starting with address ssi_strt and ending with ssi_end . the words are output msb first. the field size is set with the ssi_fsize register: 0 entire data block, 1 - 8 bit fields, 2 - 16 bit fields, 3 - 32 bit fields. the polarity of the sfr pulse can be inverted with ssi_fpol ( ssi_fpol = 0 ? srdy high - active). if srdy does not delay it, the first sfr pulse in a frame will rise on the third sclk after mux_sync (or the fourth sclk if 10mhz). mux_sync can be used to synchronize the f ields arriving at the data logger or dsp. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 49 of 104 a maxim integrated products brand functional descripti on theory of operation the energy delivered by a power source into a load can be expressed as: = t dt t i t v e 0 )( )( assuming phase angles are constant, the following formulae apply: ? p = real energy [wh] = v * a * cos * t ? q = reactive energy [varh] = v * a * sin * t ? s = apparent energy [vah] = 2 2 q p + for a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic con tent may change constantly. thus, simple rms measurements are inherently inaccurate. a modern solid - state electricity meter ic such as the 71m6513/6513h functions by emulating the integral operation above, i.e. it pr ocesses current and voltage samples through an adc at a constant frequency. as long as the adc resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied wi th the time period of sampling will yield an accurate quanti ty for the momenta ry energy. summing up the momentary energy quantities over time w ill result in accumulated energy. figure 12 : voltage. current, momentary and accumulated energy figure 12 shows the shapes of v(t), i(t), the momentary energy and the total acc umulated energy, resulting from 50 samples of the voltage and current signals over a period of 20ms. the application of 240vac and 100a res ults in an accumulation of 480ws over the 20ms period, as indicated by the curve for accumul ated energy. the described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. -500 -400 -300 -200 -100 0 100 200 300 400 500 0 5 10 15 20 time [ms] v [v], i [a], p [ws] current [a] voltage [v] energy per interval [ws] accumulated energy [ws] downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 50 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand system timing summary figure 13 summarizes the timing relationships between the input mux states, the ce_b usy signal, and the two serial output streams. in this example, mux_div =0 (six mux states) and fir_len = 0 (2 c k32 cycles). since fir filter conversions require two or three ck32 cycles, the duration of each mux cycle is 1 + 2 * states defined by mux_div if fir_len = 0, and 1 + 3 * states defined by mux_div if fir_len = 1. followed by the conversions is a single ck 32 cycle. each ce program pass begins when mux_sync falls. depending on the length of the ce program, it may continue running until the end of the adc5 conversion. ce opcodes are constructed to ens ure that all ce code passes consume exactly the same numbe r of cycles. the result of each adc conversion is inserted into the ce dram when the conversion is complete. the ce code is designed to tolerate sudden changes in adc data. the exact ck count when each adc value i s loaded into dram is shown in figure 13 . figure 13 also shows that the two serial data streams, rtm and ssi, begin transmitting at the beginning of mux_sync. rtm, consisting of 140 ck cycles, will always finish before the next code pass starts. the ssi port begins transmitting at the same time as rtm, but may significantly overrun the next code pass if a large block of dat a is required. neither the ce nor the ss i port will be affected by this overlap. ck32 mux state 00 1 2 3 4 5 mux_div conversions ( mux_div =6 is shown) settle adc mux frame adc execution s mux_sync s ce_execution rtm 140 ssi max ck count begin ssi transfer last ssi transfer 0 300 150 600 900 1200 1500 1800 adc0 adc1 adc2 adc3 adc4 adc5 ck count = ce_cycles + floor(ce_cycles + 2) / 5) notes: 1. all dimensions are 5mhz ck counts. 2. the precise frequency of ck is 150*crystal frequency = 4.9152mhz. 3. xfer_busy occurs once every (presamps * sum_cycles) code passes. ce_busy xfer_busy initiated by a ce opcode at end of sum interval adc timing ce timing rtm and ssi timing figure 13 : timing relationship between adc mux, ce, and serial transf ers figure 14 , figure 15 , and figure 16 show the rtm and ssi timing, respectively. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 51 of 104 a maxim integrated products brand cktest tmuxout/rtm flag rtm data0 (32 bits) lsb sign lsb sign rtm data1 (32 bits) lsb lsb sign sign rtm data2 (32 bits) rtm data3 (32 bits) 0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31 flag flag flag mux_sync ck32 figure 14 : rtm output format sclk (output) ssdata (output) sfr (output) srdy (input) 31 30 16 15 1 0 31 ssi_beg 30 16 15 1 0 31 ssi_beg +1 1 0 ssi_end if 16bit fields if 32bit fields if ssi_ckgate =1 if ssi_ckgate =1 mux_sync figure 15 : ssi timing, ( ssi_fpol = ssi_rdypol = 0) sclk (output) ssdata (output) sfr (output) srdy (input) 31 30 16 15 14 13 16 16 16 12 29 18 17 next field is delayed while srdy is low figure 16 : ssi timing, 16 - bit field example (external device delays srdy) sfr is the framing pulse. although ce words are always 32 bits, the ssi inter face will frame the entire data block as a singl e field, as multiple 16 - bit fields, or as multiple 32 - bit fields. the sfr pulse is one sclk clock cycle wide, changes state on the rising edge of sclk and precedes the first bit of each field. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 52 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand data flow the data flow between ce and mpu is shown in figure 17 . in a typical application, the 32 - bit compute engine (ce) sequentially processes the samples from the voltage inputs on pins ia, va, i b, vb, ic, and vc performing calculations to measure active power (wh), reactive power (varh), a 2 h, and v 2 h for four - quadrant metering. these measurements are then accessed by the mpu, processed further and output using the peripher al devices available to the mpu. figure 17 : mpu/ce data flow ce/mpu communication figure 18 shows the functional relationship between ce and mpu. the ce is contro lled by the mpu via shared registers in the i/o ram and by registers in the ce dram. the ce outputs two interrupt signals to the m pu: ce_busy and xfer_busy, whic h are connected to the mpu interrupt service inputs as external interrupts. ce_b usy indicates that the ce is actively processing data. this signal will occur once every multiplexer cycle. xfer_busy indicates that the ce is updating data to the output region of the ce ram. this will occur whenever the ce has finished generating a sum by completing an accumulation interval determined by sum_cycles * pre_samps samples. interrupts to the mpu occur on the falling edges of the xfer_busy and ce_busy signals. figure 19 shows the sequence of events between ce and mpu upon reset or power - up. in a typical application, the sequence of events is as follows: 1) upon power - up, the mpu in itializes the hardware, including disabling the ce 2) the mpu loads the code for the ce into the ce pram 3) the mpu loads ce data into the ce dram. 4) the mpu starts the ce by setting the ce_en bit in the i/o ram. 5) the ce then repetitively executes its code, generat ing results and storing them in the ce dram it is important to note that the length of the accumulation inte rval, as determined by n acc , the product of sum_cycles and pre_samps is not an exact multiple of 1000ms. for example, if sum_cycles = 60, and pre_samps = 00 (42), the resulting accumulation interval is: ms hz hz f n s acc 75 . 999 62 . 2520 2520 13 32768 42 60 = = ? = = this means that accurate time measurements require the rtc. ce mpu pre - processor post- processor irq processed metering data pulses i/o ram (configuration ram) samples data downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 53 of 104 a maxim integrated products brand figure 18 : mpu/ce communication (functional) the mpu will wait for the ce to signal that fresh data is ready (the xfer interrupt). it will read the data and perform additional processing such as energy accumulation. figure 19 : mpu/ce communication (processing sequence) fault, reset, power - up reset mode: w hen the resetz pin is pulled low or when v1 < vbias, all digital activity in the chip stops while analog circuits are still active. the oscillator and rtc module continue to run. additionally, all i/o ram bits are cleared. as long as v1, t he input voltage at the power fault block, is greater than vbias, the internal 2.5v regulator will continue to provide power to the digital section. once initiated, the reset mode will persist until the reset timer times out, s ignified by wake rising. this will occur in 41 00 cycles of the real time clock after resetz goes high, at which time the mpu will begin executing its pre boot and boot sequences from address 00. see the security section for more descr iption of preboot and boot. i/o ram (configuration ram) mpu ce pulses data interrupts display (me- mory-mapped lcd segments) dio eeprom (i2c) serial (uart0/1) samples apulsew apulser var (dio7) w (dio6) varsum wsum adc ext_pulse ce_busy xfer_busy mux ctrl. ce_en ce pram computation engine ce dram flash mpu xfer interrupt downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 54 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand power - up: after power - up, the 71m6513/6513h is in reset as long as v1 < vbias. as soon as v1 exceeds vbias, the reset timer is started which takes the mpu out of reset after 4100 oscillator cy cles (see figure 20 ). the mpu then initiates its pre - boot phase lasting 32 cycles. the supply current will be low but not zero during power - up. it will increase, once v1 exceeds vbias and will increase to the nominal value once the preboot phase starts. the supply current may then be reduced under firmware control, following the steps specified in battery ope ration and power save modes. figure 20 : timing diagram for voltages, current and operation modes af ter power - up battery operation when v1 is lower than vbias, the external battery will power t he following parts of the 71m6513/6513h: ? rtc ? crystal oscillator circuitry ? mpu xram ? wd_ovf bit power save modes in normal mode of operation, running on 3.3v supply, various resources of the 71m6513/6513h may be shut down by the mpu firmware in order to reduce power consumption while other essential resources such as uarts may remain active. table 59 outlines these resources and their typical current consumption (bas ed on initial condition mpu_div = 0). power saving measure software control typical savings disable the ce ce_en = 0 0.16ma disable the adc adc_dis = 1 1.8ma disable clock test output cktest ckoutdis = 1 0.6ma disable emulator clock eck_dis = 1 *) 0.1ma set flash read pulse timing to 33 ns flash66z =1 0.04ma disable the lcd voltage boost circuitry lcd_bsten = 0 0.9ma disable rtm outputs rtm_en = 0 0.01ma increase the clock divider for the mpu mpu_div = x 0.4ma/mhz *) this bit is to be used with caution! inadvertently setting this bit will inhibit access to the part with the ice interface and thus preclude flash erase and programming operations. table 59 : power saving measures v3p3 v1 supply current 3.3v 1.5v pre- boot reset timer firmware has control over chip... 1ms 0v v2p5 power down v1 > vbias pwr up 0ma nominal 125ms downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 55 of 104 a maxim integrated products brand temperature compensation internal compensation: the internal voltage reference is calibrated during device manufact ure. trim data is stored in on - chip fuses. for the 71m6513, the temperature coefficients tc1 and tc2 are given as c onstants that represent typical com ponent behavior. for the 71m6513h, the temperature characteristics of the chip are measur ed during production and then stored in the fuse registers trimbga , trimbgb and trimm [2:0]. tc1 and tc2 can be derived from the fuses by using the relations given in the electrical specifications section. tc1 and tc2 can be further pr ocessed to generate the coefficients ppmc and ppmc2 . trimm [2:0], trimbga and trimbgb are read by first writing either 4, 5 or 6 to trimsel (0x20fd) and then reading the value of trim (0x20ff). when the ext_temp register in ce dram (address 0x38) is set to 0, the ce automatically compensates f or temperature errors by controlling the gain_adj register (address 0x2e) ba sed on the ppmc , ppmc2 , and temp_x register values. in the case of internal compensation, gain_adj is an output of the ce. external compensation : rather than internally compensating for the temperature variation, the bandgap t emperature is provided to the embedded mpu, which then may digitally compensate the power outputs. this permits a system - wide temperature correction over the entire system rather than local to the chip. the i ncorporated thermal coefficients may includ e the current sensors, the voltage sensors, and other influences. since the band gap is chopper stab ilized via the chop_en bits, the most significant long - term drift mechanism in the voltage reference is removed. when the ext_temp register in ce dram is set to 15, the ce ignores the ppmc , ppmc2 , and temp_x register values and applies the gain supplied by the mpu in gain_adj . external compensation enables the mpu to control the ce gain based on any variable, and when ext_temp = 15, gain_adj is an input to the ce. chopping circuitry as explained in the hardware section, the bits of the i/o ram regist er chop_en [1:0] have to be toggled in between multiplexer cycles to achieve the desired elimination of dc offset . the amplifier within the reference is auto - zeroed by means of an internal signal that is controlled by the chop_en bits. when this signal is high, the connection of the amplifier inputs is reversed. this preserves the overall polarity of the amplifier gain but inverts the input offset. by alternately reversing the conn ection, the offset of the amplifier is averaged to zero. the two bits of the chop_en register have the function specified in table 60 . chop_en [1] chop_en [0] function 0 0 toggle chop signal 0 1 reference connection positive 1 0 reference connection reversed 1 1 toggle chop signal table 60 : chop_en bits for automatic chopping, the chop_en bits are set to either 00 or 11. in this mode, the polarity of the signals feeding the reference amplifier will be automatically toggled for each multiplexer cyc le as shown in figure 21 . with an even number of multiplexer cycles in each accumulation interval, the number of cy cles with positive reference connection will equal the numb er of cycles with reversed connection, and the offset for each sampled signal will be av eraged to zero. this sequence is acceptable when only the primary signals (meter voltage, meter curr ent) are of interest. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 56 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand figure 21 : chop polarity w/ automatic chopping if temperature compensation or accurate reading of the die temperature is required, alternate multiplexer cycles have to be inserted in between the regular cycles. this is done under mpu firmware control by asserting the mux_alt bit whenever necessary. since die temperature usually changes very slowly, alternat e multiplexer cycles have to be inserted very infrequently. usually, an alternate multiplexer cycle is inserted once for every accumulation period, i.e. after each xfer_busy interrupt. this sequence is shown in figure 22 . figure 22 : sequence with alternate multiplexer cycles this sequence has the disadvantage that the alternate multiplexer cycle is alwa ys operated with positive connection. consequently, dc offset will appear on the temperature measurement, which wil l decrease the accuracy of this measurement and thus cause temperature reading and compensation to be less accurate. the sequence shown in figure 23 uses the chop_en bits to control the chopper polarity after each xfer_busy interrupt . chop_en is controlled to alternate between 10 (positive) and 01 (reversed) for the f irst multiplexer cycle foll owing each accumulation interval m mux cycle n mux cycle 2 mux cycle 3 chop polarity positive positive positive positive re- versed re- versed re- versed re- versed mux cycle n mux cycle 1 mux cycle 1 mux cycle 1 accumulation interval m+1 ce_busy interrupt (falling edge) xfer_busy interrupt (falling edge) accumulation interval m+2 positive positive re- versed accumulation interval m mux cycle n mux cycle 2 mux cycle 3 chop polarity positive positive positive positive re- versed re- versed re- versed re- versed mux cycle n accumulation interval m+1 alt. mux cycle alt. mux cycle alt. mux cycle ce_busy interrupt xfer_busy interrupt accumulation interval m+2 positive positive re- versed mux_alt downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 57 of 104 a maxim integrated products brand xfer_busy interrupt. after these first two cycles, chop_en returns to 11 (automatic toggle). the value of chop_en , when set after the xfer_busy interrupt, is in force for the entire followin g multiplexer cycle. when using this sequence, the alternate multiplexer cycle is toggled betwee n positive and reversed connection resulting in accurate temperature measurement. an example for proper application of the chop_en bits can be found in the demo code shipped with the 6513 demo kits. firmware impleme ntations should closely follow this example. figure 23 : sequence with alternate multiplexer cycles and controlled chopping internal/external pulse generation and pulse counting the ce is the source for pulses. it can generate pulses directl y based on the voltage and current inputs and the configured pulse generation parameters. this is called internal pulse generati on, and applies when the ce ram register ext_pulse (address 0x37) equals 0. alternatively, the ce can be configured to generate pulses based on r egisters that are controlled by the mpu (external pulse generation), i.e. when the register ext_pulse equals 15. in the case of external pulse generation, the mpu writes values to the ce registers apulsew (0x26) and apulser (0x27). the pulse rate, usually inversely expressed as kh (and measured in wh per pulse), is determined by the ce ram registers wrate , pulse_slow , pulse_fast , in_8 , as well as by the sensor scaling vmax and imax per the equation: ] / [ 8_ 1782 .66 pulse wh x n wrate in imax vmax kh acc ? ? ? ? ? = where in_8 is the gain factor (1 or 8) controlled by the ce variable in_shunt , x is the pulse gain factor controlled by the ce variables pulse_slow and pulse_fast n acc is the accumulation count ( pre_samps * sum_cycles ) alt. mux cycle alt. mux cycle alt. mux cycle accumulation interval m accumulation interval m+1 positive positive positive positive positive accumulation interval m+2 positive positive re- versed re- versed re- versed re- versed re- versed mux cycle 2 mux cycle 2 mux cycle 2 mux cycle 3 mux cycle 3 mux cycle 3 mux cycle n mux cycle n mux cycle n chop polarity 01 11 01 11 (11) (11) (11) (11) (11) (11) (11) 10 11 (11) chop_en (11) ce_busy interrupt xfer_busy interrupt mux_alt downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 58 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand program security when enabled, the security feature limits the ice to global flash erase operat ions only. all other ice operations are blocked . this guarantees the security of the users mpu and ce program code. security is enabled by mpu code that is executed in a 32 cycle preboot interval before the primary boot sequence begins. once security is enabled, the only way to disable it is to perform a global erase of the flash memory, followed by a chip re set. global flash erase also clears th e ce pram. the first 32 cycles of the mpu boot code are called the preboot phase bec ause during this phase the ice is inhibited. a read - only status bit, preboot (sfr 0xb2[7]), identifies these cycles to the mpu. upon comple tion of the preboot sequence, the ice can be enabled and is permitted to take control of the mpu. secure (sfr 0xb2[6]), the security enable bit, is reset whenever the mpu is rese t. hardware associated with the bit permits only ones to be written to it. thus, preboot code may set secure to enable the security feature but may not reset it. once secure is set, the preboot code is protected and no external read of program code is possible. specifically, when secure is set: ? the ice is limited to bulk flash erase only. ? page zero of flash memor y, the preferred location for the users preboot code, may not be page - erased by either mpu or ice. page zero may only be erased with global flash erase. note that global flash erase erases ce program ram whether secure is set or not. ? writes to page zero, whether by mpu or ice, are inhibited. the secure bit is to be used with caution! inadvertently setting this bit will inhibit access to the part v ia the ice interface, if no mechanism for actively resetting the part between reset and erase operations is p rovided (see ice interface description). additionally, by setting the i/o ram register eck_dis to 1, the emulator clock is disabled, inhibiting access to the program wit h the emulator. see the cautionary note in the i/o ram register description! downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 59 of 104 a maxim integrated products brand firmware interface i/o ram map C in numerical order not used bits are blacked out and contain no memory and are read by t he mpu as zero. reserved bits are in use and should not be changed. name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 configuration: ce0 2000 equ[2:0] ce_en tmux[3:0] ce1 2001 pre_samps[1:0] sum_cycles[5:0] ce2 2002 mux_div[1:0] chop_en[1:0] rtm_en wd_ovf ex_rtc ex_xfr comp0 2003 comp_int[1:0] comp_stat[2:0] config0 2004 vref_cal reserved ckout_dis vref_dis mpu_div config1 2005 reserved eck_dis fir_len adc_dis mux_alt flash66z mux_e version 2006 version[7:0] digital i/o: dio0 2008 opt_txdis dio_eex dio_pw dio_pv dio1 2009 dio_r1[2:0] dio_r0[2:0] dio2 200a dio_r3[2:0] dio_r2[2:0] dio3 200b dio_r5[2:0] dio_r4[2:0] dio4 200c dio_r7[2:0] dio_r6[2:0] dio5 200d dio_r9[2:0] dio_r8[2:0] dio6 200e dio_r11[2:0] dio_r10[2:0] real time clock: rtc0 2015 rtc_sec[5:0] rtc1 2016 rtc_min[5:0] rtc2 2017 rtc_hr[4:0] rtc3 2018 rtc_day[2:0] rtc4 2019 rtc_date[4:0] rtc5 201a rtc_mo[3:0] rtc6 201b rtc_yr[7:0] rtc7 201c rtc_dec_sec rtc_inc_sec lcd display interface: lcdx 2020 lcd_bsten lcd_num[4:0] lcdy 2021 lcd_en lcd_mode[2:0] lcd_clk[1:0] lcdz 2022 lcd_fs[4:0] lcd0 2030 lcd_seg0[3:0] lcd1 2031 lcd_seg1[3:0] lcd2 2032 lcd_seg2[3:0] lcd3 2033 lcd_seg3[3:0] lcd39 2057 lcd_seg39[3:0] lcd40 2058 lcd_seg40[3:0] lcd41 2059 lcd_seg41[3:0] downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 60 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rtm probes: rtm0 2060 rtm0[7:0] rtm1 2061 rtm1[7:0] rtm2 2062 rtm2[7:0] rtm3 2063 rtm3[7:0] synchronous serial interface: ssi 2070 ssi_en ssi_10m ssi_ckgate ssi_fsize[1:0] ssi_fpol ssi_rdyen ssi_rdypol ssi_be g 2071 ssi_beg[7:0] ssi_end 2072 ssi_end[7:0] fuse selection registers: trimsel 20fd trimsel[7:0] trim 20ff trim[7:0] sfr map (sfrs specific to t eridian 80515) C in numerical order not used bits are blacked out and contain no memory and are read by t he mpu as zero. reserved bits are in use and should not be changed. this table lists only the sfr registers that are not generic 8051 sfr registers. name sfr addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 digital i/o: p0 80 dio_0[7:0] (port 0) dir0 a2 dio_dir0[7:0] p1 90 dio_1[7:0] (port 1) dir1 91 dio_dir1[7:0] p2 a0 dio_2[5:0] (port 2) dir2 a1 dio_dir2[5:0] interrupts and wd timer: intbits f8 int6 int5 int4 int3 int2 int1 int0 wdi e8 wd_rst ie_rtc ie_xfer flash: erase 94 flsh_erase[7:0] flshctl b2 preboot secure flsh_meen flsh_pwe pgadr b7 flsh_pgadr[6:0] serial eeprom: eedata 9e eedata[7:0] eectrl 9f eectrl[7:0] downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 61 of 104 a maxim integrated products brand i/o ram (configuration ram) C alphabetical order many functions of the chip can be controlled via the i/o ram (configur ation ram). the ce will also take some of its para - meters from the i/o ram. bits with a w (write) direction are written by the mpu into i/o ram. t ypically, they are initially stored in flash memory and copied to the i/o ram by the mpu. some of the more frequently programmed bits ar e mapped to the mpu sfr memory space. the remainin g bits are mapped to 2xxx. bits with r (read) direction can only be read by the mpu. on power up, all bits are cleared to zero unless otherwise stated. generic sfr registers are not listed. name location [bit(s)] dir description adc_dis 2005[3] r/w disables adc and removes bias current ce_en 2000[4] r/w ce enable. chop_en[1:0] 2002[5:4] r/w chop enable for the reference band gap circuit. 00: enabled 01: disabled 10: disabled 11: enabled reserved 2004[5] r/w must be 0. ckout_dis 2004[4] r/w ckout disable. when zero, cktest is an active output. comp_int[1:0] 2003[4:3] r/w two bits establishing whether a comparator state change should crea te mpu interrupts. 1: interrupt, 0: no interrupt. if 11, the comparat or outputs are xored. bit0 = comp2, bit1 = comp3 comp_stat[2:0] 2003[2:0] r three bits containing comparator output status. bit0 = comp1, bit1 = comp2, bit2 = comp3 dio_r0[2:0] dio_r1[2:0] dio_r2[2:0] dio_r3[2:0] dio_r4[2:0] dio_r5[2:0] dio_r6[2:0] dio_r7[2:0] dio_r8[2:0] dio_r9[2:0] dio_r10[2:0] dio_r11[2:0] 2009[2:0] 2009[6:4] 200a[2:0] 200a[6:4] 200b[2:0] 200b[6:4] 200c[2:0] 200c[6:4] 200d[2:0] 200d[6:4] 200e[2:0] 200e[6:4] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w connects dedicated i/o pins 0 to 11 to selectable internal resources. if more than one input is connected to the same resource, the multiple col umn below specifies how they are combined. see software users guide f or details). dio_gp resource multiple 0 none -- 1 reserved or 2 t0 (counter0 clock) or 3 t1 (counter1 clock) or 4 high priority i/o interrupt (int0 rising) or 5 low priority i/o interrupt (int1 rising) or 6 high priority i/o interrupt (int0 falling) or 7 low priority i/o interrupt (int1 falling) or dio_dir0[7:0] sfr a2 r/w programs the direction of dio pins 7 through 0. 1 indicates output. ignor ed if the pin is not configured as i/o. see dio_pv and dio_pw for special option for dio6 and dio7 outputs. see dio_eex for special option for dio4 and dio5. dio_dir1[7:0] sfr 91 r/w programs the direction of dio pins 15 through 8. 1 indicates output. ignored if the pin is not configured as i/o. dio_dir2[5:0] sfr a1[5:0] r/w programs the direction of dio pins 21 through 16. 1 indicates output. ignored if the pin is not configured as i/o. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 62 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand name location [bit(s)] dir description dio_0[7:0] dio_1[7:0] dio_2[5:0] sfr 80 sfr 90 sfr a0[5:0] r/w r/w r/w port 0 port 1 port 2 the value on the dio pins. pins configured as lcd will read zero. when written, changes data on pins configured as out - puts. pins configured as lcd or input will ignore writes. dio_eex 2008[4] r/w when set, converts dio4 and dio5 to interface with external eepro m. dio4 becomes sck and dio5 becomes bi - directional sda. lcd_num must be less than 18. dio_pv 2008[2] r/w causes varpulse to be output on dio7, if dio7 is configured as out put. lcd_num must be less than 15. dio_pw 2008[3] r/w causes wpulse to be output on dio6, if dio6 is configured as output. lcd_num must be less than 16. eedata[7:0] sfr 9e r/w serial eeprom interface data eectrl[7:0] sfr 9f r/w serial eeprom interface control eck_dis 2005[5] r/w emulator clock disable. when one, the emulator clock is disabled. this bit is to be used with caution! inadvertently setting this bit wil l inhibit access to the part with the ice inter face and thus preclude flash erase and pro gramming operations . if eck_dis is set, it should be done at least 1000ms after power - up to give emulators and programming devices enough time to complete an erase op eration. equ[2:0] 2000[7:5] r/w specifies the power equation to the ce. ex_xfr ex_rtc 2002[0] 2002[1] r/w interrupt enable bits. these bits enable the xfer_busy and the rtc_1sec interrupts to the mpu. note that if either interrupt is to be enabled, ex6 in the 80515 must also be set. fir_len 2005[4] r/w the length of the adc decimation fir filter. 1: 22 adc bits/3 ck32 cycles (384 ckfir cycles), 0: 21 adc bits/2 ck32 cycles (288 ckfir cycles) flash66z 2005[1] r/w should be set to 1 to minimize supply current. flsh_erase sfr 94 w flash erase initiate flsh_erase is used to initiate either the flash mass erase cycle or the flash page erase cycle. specific patterns are expected for flsh_erase in order to initiate the appropriate erase cycle. (default = 0x00). 0x55 C initiate flash page erase cycle. must be proceeded by a write to flsh_pgadr @ sfr 0xb7. 0xaa C initiate flash mass erase cycle. must be proceeded by a write to flsh_meen @ sfr 0xb2 and the debug (cc) port must be enabled. any other pattern written t o flsh_erase will have no effect. flsh_meen sfr b2[1] w mass erase enable 0 C mass erase disabled (default). 1 C mass erase enabled. must be re - written for each new mass erase cycle . downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 63 of 104 a maxim integrated products brand name location [bit(s)] dir description flsh_pgadr sfr b7[7:1] w flash page erase address flsh_pgadr [6:0] C flash page address (page 0 thru 127) that will be erased during the page erase cycle. (default = 0x00). must be re - written for each new page erase cycle. flsh_pwe sfr b2[0] r/w program write enable 0 C movx commands refer to xram space, normal operation (default). 1 C movx @ dptr ,a moves a to program space (flash) @ dptr . this bit is automatically reset after each byte written to flash. w rites to this bit are inhibited when interrupts are enabled. ie_xfer ie_rtc sfr e8[0] sfr e8[1] r/w interrupt flags. these flags are part of the wdi sfr register and mo nitor the xfer_busy interrupt and the rtc_1sec inter rupt. the flags are set by hardware and must be cleared by the in terrupt handler. see also wd_rst . intbits sfr f8[6:0] r interrupt inputs. the mpu may read these bits to see the input to external interrupts int0, int1, up to int6. these bits do not have any memory and are primarily intended for debug use. lcd_bsten 2020[7] r/w enables the lcd voltage boost circuit. lcd_clk[1:0] 2021[1:0] r/w sets the lcd clock frequency for com/seg pins (not the frame r ate. note: f w = ckfir/128 00: f w /2 9 , 01: f w /2 8 , 10: f w /2 7 , 11: f w /2 6 lcd_en 2021[5] r/w enables the lcd display. when disabled, vlc2, vlc1, and vlc0 are ground as are the com and seg outputs. lcd_fs[4:0] 2022[4:0] r/w controls the lcd full scale voltage, vlc2: ) 31 _ 3.0 7.0( 2 fs lcd vlcd vlc + ? = lcd_mode[2:0] 2021[4:2] r/w the lcd bias mode. 000: 4 states, 1/3 bias 001: 3 states, 1/3 bias 010: 2 states, ? bias 011: 3 states, ? bias 100: static display downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 64 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand name location [bit(s)] dir description lcd_num[4:0] 2020[4:0] r/w number of dual - purpose lcd/dio pins to be configured as lcd. this number can be between 0 and 18. the first dual - pur pose pin to be used as lcd is seg41/dio21. if lcd_num = 2, seg41 and seg 40 will be configured as lcd. the remaining seg39 to seg24 will be configured as dio19 to dio4. lcd_num seg dio 0 none dio4 - 21 1 seg41 dio4 - 20 2 seg40 - 41 dio4 - 19 3 seg39 - 41 dio4 - 18 4 seg38 - 41 dio4 - 17 5 seg37 - 41 dio4 - 16 6 seg36 - 41 dio4 - 15 7 seg35 - 41 dio4 - 14 8 seg34 - 41 dio4 - 13 9 seg33 - 41 dio4 - 12 10 seg32 - 41 dio4 - 11 11 seg31 - 41 dio4 - 10 12 seg30 - 41 dio4 -9 13 seg29 - 41 dio4 -8 14 seg28 - 41 dio4 -7 15 seg27 - 41 dio4 -6 16 seg26 - 41 dio4 -5 17 seg25 - 41 dio4 18 seg24 - 41 none lcd_seg0[3:0] lcd_seg41[3:0] 2030[3:0] 2059[3:0] r/w lcd segment data. each word contains information for from 1 to 4 time divisions of each segment. in each word, bit 0 corresponds to com0, on up to bit 3 for com3. mpu_div[2:0] 2004[2:0] r/w the mpu clock divider (from ckce). these bits may be program med by the mpu without risk of losing control. 000 - ckce, 001 - ckce/2, , 111 - ckce/2 7 mpu_div is 000 on power - up. mux_alt 2005[2] r/w the mpu asserts this bit when it wishes the mux to perform a dc conversions on an alternate set of inputs. mux_div[1:0] 2002[7:6] r/w the number of states in the input multiplexer. 00 - 6 states 01 - 4 states 10 - 3 states 11 - 2 states mux_e 2005[0] r/w mux_sync enable. when high, converts seg7 into a mux_sync output. opt_txdis 2008[5] r/w tristates the opt_tx output. preboot sfr b2[7] r indicates that the preboot sequence is active. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 65 of 104 a maxim integrated products brand name location [bit(s)] dir description pre_samps[1:0] 2001[7:6] r/w together w/ sum_cycles , this value determines the number of samples in one sum cycle between xfer interrupts for the ce. number of samples = pre_samps * sum_cycles . 00 - 42, 01 - 50, 10 - 84, 11 - 100 rtc_sec[5:0] rtc_mini[5:0] rtc_hr[4:0] rtc_day[2:0] rtc_date[4:0] rtc_mo[3:0] rtc_yr[7:0] 2015 2016 2017 2018 2019 201a 201b r/w the rtc interface. these are the year, month, day, hour, minute and second parameters for the rtc. the rtc is set by writing to these registers. year 00 is defined as a leap year. sec 00 to 59 min 00 to 59 hr 00 to 23 (00=midnight) day 01 to 07 (01=sunday) date 01 to 31 mo 01 to 12 yr 00 to 256 rtc_dec_sec rtc_inc_sec 201c[1] 201c[0] w rtc time correction bits. only one bit may be pulsed at a time. when pulsed, causes the rtc time value to be incremented (or decremented) by an additional second the next time the rtc_sec register is clocked. the pulse width may be any value. if an additional correction is desired, the mpu must wait 2 seconds before pulsing one of the bits again. rtm_en 2002[3] r/w real time monitor enable. when 0, the rtm output is low. this bit enables the two wire version of rtm rtm0[7:0] rtm1[7:0] rtm2[7:0] rtm3[7:0] 2060 2061 2062 2063 r/w four rtm probes. before each ce code pass, the values of these regist ers are serially output on the rtm pin. the rtm registers are ignored when rtm_en =0. secure sfr b2[6] r/w enables security provisions that prevent external reading of flash memory and ce program ram. this bit is reset on chip reset and may only be set. attempts to write zero are ignored. ssi_en 2070[7] r/w enables the synchronous serial interface (ssi) on seg3, seg4, and seg5 pins. if ssi_rdyen is set, seg6 is enabled also. the pins take on the new functions sclk, ssdata, sfr, and srdy, respectively. when ssi_en is high and lcd_en is low, these pins are converted to the ssi function, regardless of lcden and lcd_num . for proper lcd operation, ssi_ en must not be high when lcd_en is high. ssi_10m 2070[6] r/w ssi clock speed: 0: 5mhz, 1: 10mhz ssi_ckgate 2070[5] r/w ssi gated clock enable. when low, the sclk is continuous. when high, the clock is held low when data is not being transferred. ssi_fsize[1:0] 2070[4:3] r/w ssi frame pulse format: 0: once at beginning of ssi sequence (whole block of data), 1: every 8 bits, 2: every 16 bits, 3: every 32 bits. ssi_fpol 2070[2] r/w sfr pulse polarity: 0: positive, 1: negative ssi_rdyen 2070[1] r/w srdy enable. if ssi_rdyen and ssi_en are high, the seg6 pin is configured as srdy. otherwise, it is an lcd driver. ssi_rdypol 2070[0] r/w srdy polarity: 0: positive, 1: negative downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 66 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand name location [bit(s)] dir description ssi_beg[7:0] ssi_end[7:0] 2071[7:0] 2072[7:0] r/w the beginning and ending address of the transfer region of the ce data memory. if the ssi is enabled, a block of words starting with ssi_beg and ending with ssi_end will be sent. ssi_end must be larger than ssi_beg . the maximum number of output words is limited by the number of ssi clocks in a ce code pass see fir_len , mux_div , and ssi_10m . sum_cycles [5:0] 2001[5:0] r/w together w/ pre_samps , this value determines (for the ce) the number of samples in one sum cycle between xfer interrupts. number of samples = pre_samps * sum_cycles . tmux[3:0] 2000[3:0] r/w selects one of 16 inputs for tmuxout. 0 C dgnd (analog) 1 C ibias (analog) 2 C pll_2.5v (analog) 3 C vbias (analog) 4 C rtm (real time output from ce) 5 C wdtr_en (comparator 1 output and v1lt3) 6 C v2_ok (comparator 2 output) 7 C v3_ok (comparator 3 output) 8 C rxd (from optical interface) 9 C mux_sync (from mux_ctrl) a C ck_10m b C ck_mpu c C reserved for production test d C rtclk e C ce_busy f C xfer_busy reserved 2005[7] r/w must be zero. trimsel 20fd w selects the temperature trim fuse to be read with the trim register ( trimm [2:0] : 4, trimbga : 5, trimbgb : 6) trim 20ff r contains trimbga , trimbgb , or trimm [2:0] depending on the value written to trimsel . if trimbgb = 0 then the ic is a 6513 else the ic is a 6513h. version[7:0] 2006 r the silicon revision number. this data sheet does not apply to revis ions < 000 0100. vref_cal 2004[7] r/w brings vref out to the vref pin. this feature is disabled when vref_dis =1. vref_dis 2004[3] r/w disables the internal voltage reference. wd_rst sfr e8[7] w resets the wd timer. the wdt is reset when a 1 is written to t his bit. only byte operations on the whole wdi register should be used. wd_ovf 2002[2] r/w the wd overflow status bit. this bit is set when the wd timer overflows. it is powered by the vbat pin and at boot - up will indicate if the part is recovering from a wd overflow or a power fault. this bit should be cleared by the mpu on boot - up. it is also automatically cl eared when resetz is low. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 67 of 104 a maxim integrated products brand ce program and environment ce program the ce program is supplied by teridian as a data image that can be merged with the mpu operational code for mete r applications. typically, the ce program covers most applications and does not need to be modified. formats all ce words are 4 bytes. unless specified otherwise, they are in 32 - bit twos complement ( - 1 = 0xffffffff). calibration para meters are defined in flash memory (or external eeprom) and must be copie d to ce memory by the mpu before enabling the ce. internal variables are used in internal ce calculations. in put variables allow the mpu to control the behavior of the ce code. output variables are outputs of the ce calculations. the c orresponding mpu address for the most signi ficant byte is given by 0x1000 + 4 x ce_address and 0x1003 + 4 x ce_addre ss for the least significant byte. constants constants used in the ce data memory tables are: ? sampling frequency: f s = 32768hz/13 = 2520.62hz. ? f 0 is the fundamental signal frequency, typically 50 or 60hz. ? imax is the external rms current corresponding to 250mv peak at the inputs ia , ib, ic. ? vmax is the external rms voltage corresponding to 250mv peak at the inputs va, vb, vc. ? n acc , the accumulation count for energy measurements is pre_samps*sum_cycles . this value resides in sum_pre (ce address 36). ? accumulation count time for energy measurements is pre_samps*sum_cycles /f s . ? in_8 is a gain constant of current channel n. its value is 8 or 1 and is controlled by in_shunt . ? x is a gain constant of the pulse generators. its value is determi ned by pulse_fast and pulse_slow . ? voltage lsb = vmax * 7.879810 - 9 v. the system constants imax and vmax are used by the mpu to convert internal digital quantities (as used by the ce) to external, i.e. metering quantities. their values are determined by the scal ing of the voltage and current sensors used in an actual meter. the lsb values used in this document relate digital quan tities at the ce or mpu interface to external meter inp ut quantities. for example, if a sag threshold of 80v peak is desired at the mete r input, t he digital value that should be pro - grammed into sag_thr would be 80v/ sag_thr lsb , where sag_thr lsb is the lsb value in the description of sag_thr . the parameters equ, ce_en, pre_samps , and sum_cycles are essential to the function of the ce and are stored i n i/o ram (see i/o ram section). environment before starting the ce using the ce_en bit, the mpu has to establish the proper environment for the ce by implementing the following steps: ? loading the image for the ce code into ce pram. ? loading the ce data int o ce dram. ? establishing the equation to be applied in equ . ? establishing the accumulation period and number of samples in pre_samps and sum_cycles . ? establishing the number of cycles per adc mux cycle. there must be thirteen 32768hz cycles per adc mux cycle (see system timing diagram, figure 13 ). this means that the product of the number of cycles per adc conversion and the number of conversions per cycle mus t be 12 (al lowing for one settling cycle). the default configuration is fir_len = 0 (two cycles per conversion) and mux_div = 0 (6 conversions per mux cycle). downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 68 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand during operation, the mpu is in charge of controlling the multiplexer cycl es, for example by inserting an alternate multiplex er sequence at regular intervals using mux_alt . this enables temperature measurement. the polarity of chop must be altered for each sample. it must also alternate for each alternate multiplexer reading. the mpu must program chop_en alternately between 01 and 10 on every ce_busy interrupt except for the first ce_busy after an xfer_busy interrupt. note that when xfer_busy occurs, i t will always be at the same time as a ce_busy interrupt. operating ce codes with environment parameters deviating from the valu es specified by teridian will lead to unpredictable results. ce calculations the ce performs the precision computations necessary to accurately measure power. these computations in clude offset cancellation, phase compensation, product smoothing, product summation, freque ncy detection, var calculation, sag detection, peak detection, and voltage phase measurement. all data computed by the ce is dependent on the selected meter equation as given by equ ( in i/o ram ) . as a function of equ , the element components v0 through i2 take on different meanings. equ watt & var formula ( wsum/varsum ) element input mapping w0sum/ var0sum w1sum/ var1sum w2sum/ var2sum i0sq sum i1sq sum i2sq sum 0 va ia (1 element, 2w 1 ) va*ia - - ia - - 1 va*(ia - ib)/2 (1 element, 3w 1 ) va*(ia - ib)/2 - (ia - ib) ib - 2 va*ia + vb*ib (2 element, 3w 3 delta) va*ia vb*ib - ia ib - 3 va*(ia - ib)/2 + vc*ic (2 element, 4w 3 delta) va*(ia - ib)/2 - vc*ic ia - ib ib ic 4 va*(ia - ib)/2 + vb*(ic - ib)/2 (2 element, 4w 3 wye) va*(ia - ib)/2 vb*(ic - ib)/2 - ia - ib ic - ib ic 5 va*ia + vb*ib + vc*ic (3 element, 4w 3 wye) va*ia vb*ib vc*ic ia ib ic ce ram locations the information given in the following tables apply to ce code ver sion ce13b09d. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 69 of 104 a maxim integrated products brand ce front end data (raw data) access to the raw data provided by the afe is possible by reading addresses 0 through 7, as listed below. address (hex) name description 0x00 ia phase a current 0x01 va phase a voltage 0x02 ib phase b current 0x03 vb phase b voltage 0x04 ic phase c current 0x05 vc phase c voltage 0x06 temp temperature 0x07 v3 v3 monitor/comparator input ce status word since the ce_busy interrupt occurs at 2520.6hz, it is desirable to minimize the computation required in the inter rupt handler of the mpu. the ce status word can be read by the mpu at every ce_busy interrupt. ce address name description 0x51 cestatus see description of ce status word below the ce status word is useful for generating early warnings to the mpu. it contains s ag warnings for phase a, b, and c, as well as f0, the derived clock operating at the fundamental input fr equency. cestatus provides information about the status of voltage and input ac signal frequency, which are useful for generating an early power fail warning to initiate necessary data storage. cestatus represents the status flags for the preceding ce code pass (ce _busy interrupt). note: the ce does not store sag alarms from one code pass to the ne xt. cestatus is refreshed at every ce_busy inter rupt and remains valid for up to 100s after the ce_busy interrupt occurs. unsy nchronized read operations of cestatus will yield unreliable results. the significance of the bits in cestatus is shown in the table below: cestatus bit name description 31 - 29 not used these unused bits will always be zero. 28 f0 f0 is a square wave at the exact fundamental input frequency. 27 sag_c normally zero. becomes one when |vc| remains below sag_thr for sag_cnt samples. will not return to zero until |vc| rises above sag_thr . 26 sag_b normally zero. becomes one when |vb| remains below sag_thr for sag_cnt samples. will not return to zero until |vb| rises above sag_thr . 25 sag_a normally zero. becomes one when |va| remains below sag_thr for sag_cnt samples. will not return to zero until |va} rises above sag_thr . 24 -0 not used these unused bits will always be zero. for generating proper status information, the ce is initialized by the mpu using sag_thr (default of 80v rms at the meter input if vmax =600v) and sag_cnt (default 80 samples). using the default value for sag_cnt , the peak - to - peak signal has to b e below sag_thr value for 32 milliseconds to activate the sag_x status bits. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 70 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand ce address name default description 0x31 sag_thr +23,930,000 (0x16d23aa) meter voltage inputs must be above this threshold to prevent sag alar ms. lsb = vmax * 7.879810 - 9 v. for example, if a sag threshold of 80v rms is desired, 9 10 8798.7 2 80 _ ? ? ? = vmax thr sag 0x32 sag_cnt 80 number of consecutive voltage samples below sag_thr before a sag alarm is declared (80*397s = 31.8ms). ce transfer variables when the mpu receives the xfer_busy interrupt, it knows that fresh data is available in the transfer variabl es. ce trans fer variables are modified during the ce code pass that ends with an xfer_bus y interrupt. they remain constant throughout each accumulation interval. in this data sheet, the names of ce tr ansfer variables always end with _x. fundamental power measurement variables the table below describes each transfer variable for fundamental power measurement. all variables are signed 32 bit integers. accumulated variables such as wsum are internally scaled so they have at least 2x margin before overflow when the integration time is 1 second. additionally, the hardware will not per mit output values to fold back upon overflow. ce address name description 0x42 wsum_x the signed sum: w0sum_x+w1sum_x+w2sum_x 0x43 w0sum_x the sum of watt samples from each wattmeter element. lsb = 9.4045*10 - 13 vmax imax / in_8 wh. 0x44 w1sum_x 0x45 w2sum_x 0x46 varsum_x the signed sum: var0sum_x+var1sum_x+var2sum_x 0x47 var0sum_x the sum of var samples from each wattmeter element. lsb = 9.4045*10 - 13 vmax imax / in_8 varh. 0x48 var1sum_x 0x49 var2sum_x wsum_x and varsum_x are the signed sum of phase - a, phase - b and phase - c wh or varh values according to the metering equation specified in the i/o ram register equ . wxsum_x is the wh value accumulated for phase x in the last accumulation interval and can be computed based on the specified lsb value. for example, with vmax = 600v and imax = 208a, lsb (for wxsum_x ) is 0.1173 wh. instantaneous power measurement variables the freqsel register selects the input phase used for frequency measurement and for the main_edge counter . the frequency measurement is implemented using the frequency locked loo p of the ce for the selected phase. ixsqsum_x and vxsqsum are the squared current and voltage samples acquired during the last accumulation interv al. insqsum_x can be used for computing the neutral current. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 71 of 104 a maxim integrated products brand ce address name description 0x33 freqsel selected phase for the frequency monitor, the phase - to - phase voltage measurements, and voltage zero crossings: phase a: 0 (default) phase b: 1 phase c: 2 0x41 freq_x fundamental frequency. lsb 6 32 10 587 .0 2 ? ? s f hz 0x4a i0sqsum_x the sum of squared current samples from each element. lsb = 9.4045*10 - 13 imax 2 / in_8 2 a 2 h 0x4b i1sqsum_x 0x4c i2sqsum_x 0x4d insqsum_x the sum of squared current samples from the calculated neutral: + + 2 2 1 0 ) ( i i i . lsb = 1.2539*10 - 12 imax 2 / in_8 2 a 2 h 0x4e v0sqsum_x the sum of squared voltage samples from each element. lsb= 9.4045*10 - 13 vmax 2 v 2 h 0x4f v1sqsum_x 0x50 v2sqsum_x 0x5a v3sqsum_x the sum of squared voltage samples from the v3 input. if cal_v3 = 8192, then lsb = 9.4045*10 - 13 vmax 2 v 2 h or 9.4045*10 - 13 imax 2 i 2 h the rms values can be computed by the mpu from the squared current and voltage samples as per the formulae: other measurement parameters ph_atob_x and ph_atoc_x contain phase angle information between the phase voltages, depending on the setti ng of freq_sel , as shown in the table below. the phase angle information can be used for phase sequencing and error detection. if the voltage at the selected phase is missing, the meter accur acy will be reduced. to maintain accuracy, freq_sel must be set to a phase with an active voltage. for example, in a system where phase a is lost (which can be detected using the sag bits or by comparing the voltage va with a lower limit), freq_sel must be set to an alternative phase to maintain accuracy. mainedge_x is useful for implementing a real - time clock based on the input ac signal. ma inedge_x is the number of half - cycles accounted for in the last accumulated interval for the a c signal of the phase specified in the freq_sel register. acc s rms n f lsb vxsqsum vx ? ? ? = 3600 acc s rms n f lsb ixsqsum ix ? ? ? = 3600 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 72 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand ce address name description frequ_sel = 0 frequ_sel = 1 frequ_sel = 2 0x52 ph_atob_x phase lag from va to vb. phase lag from vb to vc. phase lag from vc to va. angle in degrees ph_atob_x *360/n acc +2.4 ph_atob_x *360/n acc +2.4 ph_atob_x *360/n acc - 4.8 0x53 ph_atoc_x phase lag from va to vc. phase lag from vb to va. phase lag from vc to vb. angle in degrees ph_atoc_x *360/n acc +4.8 ph_atoc_x *360/n acc - 2.4 ph_atoc_x *360/n acc - 2.4 0x55 mainedge_x the number of zero crossings of va in the pre - vious accumulation inter val. the number of zero crossings of vb in the pre - vious accumulation inter val. the number of zero crossings of vc in the pre - vious accumulation inter val. edge crossings are either direction and are debounced. temperature measurement and temperature compensation input variables: temp_nom is the reference value for temperature measurement, i.e. when this val ue is set with temp_raw_x at known temperature. the 71m6513/6513h measures temperature with ref erence to this value. degscale is the slope or rate of temperature increase or decrease fr om the temp_nom for temp_x measurement. ppmc and ppmc2 are temperature compensation coefficients. their values should reflect the characteristics of the band gap voltage reference of the chip. ppmc and ppmc2 follow the square law characteristics to compensate for nonlinear temperature behaviors, when the 71m6513/6513h is in internal temperature compensation m ode. ext_temp allows the mpu to select between direct control of gain_adj or management of gain_adj by the ce, based on temp_x and the temperature correction coefficients ppmc and ppmc2 . downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 73 of 104 a maxim integrated products brand ce address name default description 0x11 temp_nom 0 during calibration, the value of temp_raw_x should be placed in temp_nom . 0x30 degscale 22721 scale factor for temp_x . temp_x = - degscale *2 - 22 *( temp_raw_x - temp_nom ). 0x38 ext_temp 0 should be 15 or 0. when 15, causes the ce to ignore internal tem perature compensation and permits the mpu to control gain_adj . when internal temperature compensation is selected, gain_adj will be: ? ?? ? ? ?? ? ? + ? + + = 23 2 14 2 2 _ 2 _ 1 16384 _ ppmc x temp ppmc x temp floor adj gain default is 0 (internal compensation). 0x39 ppmc 0 linear temperature com pensation factor. equals the linear temperature co - efficient (ppm/c) of vref multiplied by 26.84, or tc1 (express ed in v/c, see electrical specifications) multiplied by 22.46 1 . a positive value will cause the meter to run faster when hot. the compensation factor affects both v and i and will therefore have a double effect on products. 1 ce scaling factor 22.46=2 21 /( 1.195*5 7 ) 0x3a ppmc2 0 square - law temperature compensation factor. equals the square - law tem - perature coefficient (ppm/c 2 ) of vref multiplied by 1374, or tc2 (ex - pressed in v/c 2 , see electrical specifications) multiplied by 1150 2 .1 . a po - sitive value will cause the meter to r un faster when hot. the compensa tion factor affects both v and i and will therefore have a double effec t on prod - ucts. 2 ce scaling factor 1150=2 29 /(1.195*5 8 ) output variables: temp_x is the temperature measurement from reference temperature of temp_nom . temp_x is computed using temp_raw_x and degscale . this quantity is positive when the temperature is above the reference and is negative for cold temperatures. temp_raw_x is the raw processed value from adc output and is the fundamental quantity for tem perature measurement. temp_raw_x is less than temp_nom at higher temperatures. temp_raw_x is more than temp_nom for cooler temperatures than reference temperature. gain_adj is a scaling factor for power measurements based on temperature (when in internal temperature compensation mode). in general, for higher temperatures it is lower than 16384 and higher than 16384 for lower temperatures. gain_adj is mainly dependent on the ppmc , ppmc2 and temp_x register values. this parameter is automatically computed by the ce and is used by the ce for temperature compensation. ce address name description 0x40 temp_x deviation from calibration temperature. lsb = 0.1 0 c. 0x54 temp_raw_x filtered, unscaled reading from temperature sensor. this value should be written to temp_nom during meter calibration. 0x2e gain_adj scales all voltage and current inputs. 16384 provides unity gain. default is 16384 . if ext_tmp = 0, gain_adj is updated by the ce. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 74 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand pulse generation input variables: the combination of the pulse_slow and pulse_fast parameters control the speed of the pulse rate. the default values of 1 and 1 will maintain the original pulse rate given by the kh equation. wrate controls the number of pulses that are generated per measured wh and varh quantities. the lower wrate it is the slower is the pulse rate for measured power quantity. the metering constant k h is derived from wrate as the amount of energy measured for each pulse. that is, if kh = 1wh/pulse, a power applied to the meter of 120v and 30a results in one pulse per second. if the load is 240v at 150a, ten pulses per second wil l be generated. control is transferred to the mpu for pulse generation if ext_pulse > 0. in this case, the pulse rate is determined by apulsew and apulser . the mpu has to load the source for pulse generation in apulsew and apulser to generate pulses. irrespective of the ext_pulse , status the output pulse rate controlled by apulsew and apulser is implemented by the ce only. by setting ext_pulse > 0, the mpu is providing the source for pulse generation. if ext_pulse is negative, w0sum_x and var0sum_x are the default pulse generation sources. in this case, creep cannot be controlled since it is an mpu function. the maximum pulse rate is 3*f s = 7.56khz. pulse_width allows adjustment of the pulse width for compatibility with calibration and ot her external equipment. the minimum pulse width possible is 66.16s. the maximum time jitter is 1/6 of the mux cycle period (normally 67s) and is independent of the number of pulses measured. thus, if the pulse generator is monitored for 1 second, the peak jitter is 67ppm. after 10 seconds, the peak jitter is 7ppm. the average jitter is always zero. if it is attempted to drive either pulse gener ator faster than its maximum rate, it will simply output at its maximum rate without exhibiting any roll - over characteristics. the actual pulse rate, using wsum as an example, is: hz f wsum wrate x rate s 46 2 ? ? ? = where f s = 2520.6hz (sampling frequency), and x = pulse speed factor derived from ce variables pulse_slow and pulse_fast (see table below). downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 75 of 104 a maxim integrated products brand ce address name default description 0x28 pulse_slow 1 when pulse_slow > 0, the pulse generator input is reduced 64x. when pulse_fast > 0, the pulse generator input is increased 16x. these two parameters control the pulse gain factor x (see table below ). allowed values are either 1 or C 1. x pulse_slow pulse_fast 1.5 * 2 2 = 6 - 1 - 1 1.5 * 2 6 = 96 -1 1 1.5 * 2 - 4 = 0.09375 1 -1 1.5 1 (default) 1 (default) 0x29 pulse_fast 1 0x2d wrate 683 kh = vmax * imax *66.1782 / ( in_8 * wrate *n acc *x) wh/pulse. 0x36 sum_pre 2520 pre_samps * sum_cycles (n acc ) 0x37 ext_pulse 15 should be 15 or 0. when zero, causes the pulse generators to respond to wsum_x and varsum_x. otherwise, the generators respond to values the mpu places in apulsew and apulser . 0x3c pulse_width 50 the maximum pulse width (low - going pulse) is: (2 * pulse_wi dth + 1) * 66s. 0 is a legitimate value. 0x26 apulsew 0 wh pulse generator input, to be updated by the mpu when using external pulse generation (see dio_pw bit). the output pulse rate is: apulsew * f s * 2 - 32 * wrate * 2 - 14 this input is buffered and can be updated by the mpu during a computation interval. the change will take effect at the beginning of the nex t interval. 0x27 apulser 0 varh pulse generator input, to be updated by the mpu when using external pulse generation (see dio_pv bit). the output pulse rate is: apulser * f s *2 - 32 * wrate * 2 - 14 this input is buffered and can be updated by the mpu during a computation interval. the change will take effect at the beginning of the nex t interval. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 76 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand ce calibration parameters the table below lists the parameters that are typically entered to effect calibration of meter accuracy. ce address name default description 0x08 cal_ia 16384 these constants control the gain of their respective channels. the nominal value for each parameter is 2 14 = 16384. the gain of each channel is directly proportional to its cal parameter. thus, if the gain of a channel is 1% slow, cal should be increased by 1%. 0x09 cal_va 16384 0x0a cal_ib 16384 0x0b cal_vb 16384 0x0c cal_ic 16384 0x0d cal_vc 16384 0x65 cal_v3 8192 gain control for v3 channel, used for neutral current measurement. 0x0e phadj_a 0 these three constants control the ct phase compensation. no com pensation occurs when phadj_x = 0. as phadj_x is increased, more compensation (lag) is introduced. range: 2 15 C 1. if it is desired to delay the current by the angle : ? ? ? = tan tan x phadj 0131 .0 1487 .0 02229 .0 2 _ 20 at 60hz ? ? ? = tan tan x phadj 009695 .0 1241 .0 0155 .0 2 _ 20 at 50hz 0x0f phadj_b 0 0x10 phadj_c 0 0x11 temp_nom n/a during calibration, the value of temp_raw_x should be placed in temp_nom . downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 77 of 104 a maxim integrated products brand other ce parameters the table below shows ce parameters used for suppression of noise due to scalin g and truncation effects as well as scaling factors. ce address name default description 0x2f quant 0 this parameter is added to the watt calculation to compensate for input noise and truncation. lsb=( vmax * imax / in_8 ) *1.04173*10 -9 w 0x34 quant_var 0 this parameter is added to the var calculation to compensate for input noise and truncation. lsb = ( vmax * imax / in_8 ) * 1.04173*10 -9 w 0x35 quant_i 0 this parameter is added to compensate for input noise and truncation in the squaring calculations for i 2 and v 2 . lsb= vmax 2 *1.04173*10 -9 v 2 lsb= ( imax 2 / in_8 2 )*1.04173*10 -9 a 2 0x3b kvar 6448 scale factor for the var calculation. the default value of kvar should never need to be changed. 0x64 quant_v3 0 offset for low - current measurement on v3. lsb = = 9.4045*10 - 13 imax 2 a 2 h typical performance data wh accuracy at room temperature figure 24 : wh accuracy, 0.3a - 200a/240v varh accuracy at room temperature 200 100 30 25 10 3 1 0.3 - 0.2 - 0.15 - 0.1 - 0.05 0 0.05 0.1 0.15 0.2 0.1 1 10 100 1000 %error a 0 deg 60 deg - 60 deg 180 deg downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 78 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand figure 25 : varh accuracy for 0.3a to 200a/240v performance harmonic performance test performed at current distortion amplitude of 40% and voltage distortion amplit ude of 10% as per iec 62053, part 22. figure 26 : meter accuracy over harmonics at 240v, 30a 200 100 30 25 10 3 1 0.3 - 0.2 - 0.15 - 0.1 - 0.05 0 0.05 0.1 0.15 0.2 0.1 1 10 100 1000 % error a 90 deg 150 deg 270 deg -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 1 3 5 7 9 11 13 15 17 19 21 23 25 harmonic error [%] 50hz harmonic data 60hz harmonic data downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 79 of 104 a maxim integrated products brand application informat ion connection of sensors (ct, resistive shunt, rogowski coil) figures 27 through 30 show how resistive dividers, current transformers, res tive shunts, and rogowski coils are connected to the voltage and current inputs of the 71m6513. the analog input pins of the 7 1m6511 are designed for sensors with low source impedance. rc filters with resistance values higher than those implemented in the teridian demo boards shoul d be avoided. figure 27 : resistive voltage divider (left), current transformer (ri ght) figure 28 : resistive shunt (left), rogowski coil (right) distinction between 71m6513 and 71m6513h parts 71m6513h parts go through a process of trimming and characterization during production that make them suitable to high - accuracy appli cations. the first process applied to the 71m6513h is the trimming of the r eference voltage, which is guaranteed to have accuracy over temperature of better that 10ppm/c. the second process applied to the 71m6513h is the characterization of the reference voltage ove r temperature. the coefficients for the reference voltage are stored in so - called trim fuses (i/o ram registers trimbga , trimbgb , trimm [2:0]. the mpu program can read these trim fuses and calculate the correc tion coefficients ppm1 and ppm2 pe r the formulae given in the performance specifications section (vref, vbias). s ee the temperature compensation section for details. the fuse trimbgb is non - zero for the 71m6513h part and zero for the 71m6513 part. trim fuse information is not available for non - h parts. thus, the standard settings are to be applied. these sett ings are: ? ppmc = tc1 * 22.46 = C 149 ? ppmc2 = tc2 * 1150.1 = C 392 va = vin * r out /(r out + r in ) v in r in r out va vout = di in / dt v out r 1/n i in v c v3p3 ia vout = di in / dt v out r downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 80 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand temperature compensation and mains frequency stabilization for the rtc the accuracy of the rtc depends on the stability of the external crysta l. crystals vary in terms of initial accuracy as well as i n terms of behavior over temperature. the flexibility provided by t he mpu allows for compensation of the rtc using the sub - strate temperature. to achieve this, the crystal has t o be characterized over temperature and the three coefficients y_cal , y_calc , and y_cal_c2 have to be calculated. provided the ic substrate temperatures tr acks the crystal temperature, the coefficients can be used in the mpu firmware to trigger occasional corrections of the rtc seconds count, using the rtc_dec_sec or rtc_inc_sec registers in i/o ram. it is not recommended to measure crystal frequency directly due to the error i ntroduced by the measurement probes. a practical method to measure the crystal frequency (when installed on the pcb with the 71m6513) is to have a dio pin toggle every second, based on the rtc interrupt, with all other interrupt s disabled. when this signal is measured with a precision timer, the crystal frequency can be obtained from the measured time period t (in s): t s f 6 10 32768 = example: let us assume a crystal characterized by the measurements shown in table 61 . the values show that even at nominal temperature (the temperature at which the chip was calibrated for ene rgy), the de viation from the ideal crystal frequency is 11.6 ppm, resulting in about one second inaccuracy per day, i.e. more than some standards allow. deviation from nominal temperature [c] measured frequency [hz] deviation from nominal frequency [ppm] +50 32767.98 - 0.61 +25 32768.28 8.545 0 32768.38 11.597 - 25 32768.08 2.441 - 50 32767.58 - 12.817 table 61 : frequency over temperature as figure 29 shows, even a constant compensation would not bring much improvement, since the temperature characteristics of the crystal are a mix of constant, linear, and quadratic effec ts (in commercially available crystals, the constant and quadrati c effects are dominant). figure 29 : crystal frequency over temperature the temperature characteristics of the crystal are obtained from the curve in figure 29 by curve - fitting the ppm deviations. a fairly close curve fit is achieved with the coefficients a = 10 .89, b = 0.122, and c = C 0.00714 (see figure 30 ). 32767.5 32767.6 32767.7 32767.8 32767.9 32768 32768.1 32768.2 32768.3 32768.4 32768.5 -50 -25 0 25 50 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 81 of 104 a maxim integrated products brand when applying the inverted coefficients, a curve (see figure 30 ) will result that eff ectively neutralizes the original crystal characteristics. the frequencies were calculated using the fit c oefficients as follows: ? ? ? ? ? ? + + + ? = 6 2 6 6 10 10 10 1 c t b t a f f nom figure 30 : crystal compensation the mpu demo code supplied with the teridian demo kits has a direct interface for these coefficients and it directly con trols the rtc_dec_sec or rtc_inc_sec registers. the demo code uses the coefficients in the following form: 1000 2 _ 100 _ 10 _ ) ( 2 calc y t calc y t cal y ppm correction ? + ? + = note that the coefficients are scaled by 10, 100, and 1000 to provide more resolution. for our example case, the coefficients would then become (after rounding, since the demo code accepts only integers): y_cal = 109, y_calc = 12, y_calc2 = 7 alternatively, the mains frequency may be used to sta bilize or check the function of the rtc. for this purpose, the ce provides a count of the zero crossings detected for the selected line voltage in the main_edge_x address. this count is equivalent to twice the line frequency, and can be used to synchroniz e and/or correct the rtc. external temperature compensation in a production electricity meter, the 71m6513 or 71m6513h is not the only component contr ibuting to temperature de - pendency. in fact, a whole range of components (e.g. current transformers, r esistor dividers, power sources, filter capacitors) will exhibit slight or pronounced temperature effects. since the output of the on - chip temperature sensor is accessible to the mpu, temperature - compensation mechanisms with great flexibility, i.e. beyond the capabilities implemented in the ce, are possible. temperature measurement temperature measurement can be implemented with the following steps: 1) at a known temperature t n , read the temp_raw register of the ce and write the value into temp_nom . 2) read the temp_x register at the known temperature. the obtained value should be < 0.1c. 3) the temperature t (in c) at any environment can be obtained by r eading temp_x and applying the following formula: 32767.5 32767.6 32767.7 32767.8 32767.9 32768 32768.1 32768.2 32768.3 32768.4 32768.5 -50 -25 0 25 50 crystal curve fit inverse curve 10 _ x temp t t n + = downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 82 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand temperature compensation for the 71m65 1 3 (regular accuracy parts), the temperature coefficient s tc1 and tc2 are given as constant s that represent typical com ponent behavior (in v/c 2 ). tc1 and tc2 allow compensation for variations of the reference voltage to within 40 ppm/c. for the high - accuracy parts, individualized coefficients tc1 and tc2 can be re trieved from the on - chip fuses via trimbga , trimbgb , trimm[2:0] (see section distinction between 71m6513 and 71m6513h parts ). for th e 71m6513h, tc1 and tc2 allow compensation for variations of the reference voltage to within 1 0 ppm/c since tc1 and tc2 are given in v/c and v/c 2 , respectively, the value of the vref voltage (1.195v) has to be taken into account when transitioning to ppm/c and ppm/c 2 . this means that ppmc = 26.84*tc1/1.195 and ppmc2 = 1374*tc2/1.195). close examination of the electrical specification (see table 62 ) for the 71m6513 reveals that the achievable deviation is not strictly 40 ppm/c over the whole temperature range: only for temperatures for which t - 22 > 40 (i.e. t > 62c) or for which t- 22 < - 40 (i.e. t < - 18c), the data sheet states 40 ppm/c. for temperatures between - 18c and +62c, the error should be considered constant at 1,600 ppm, or 0.16%. similar considerations apply to the high - accuracy part 71m6513h (see table 63 ), where the error around the calibration temperature should be considered constant at 600 ppm, or 0.06%. table 62 : vref definition for the regular accuracy parts 71m6513 p arameter m in t yp vref(t) deviation from vnom(t) )40,22 max( 10 )( )( )( 6 ? ? t t vnom t vnom t vref - 40 +40 ppm /oc table 63 : vref definition for the high - accuracy parts 71m6513h p arameter m in t yp vref(t) deviation from vnom(t) )40,22 max( 10 )( )( )( 6 ? ? t t vnom t vnom t vref -10 +1 0 ppm /oc figure 31 and figure 32 show this concept graphically. the box from - 18c to +62c reflects the fact that it is impractical to measure the temperature coefficient of high - quality references at small temperature excursions. for example, at +25c, the expected error would be 3c * 40 ppm/c, or just 0.012% for the regular - accuracy parts. the maximum deviation of 2520 ppm (or 0.252%) for the regular - accuracy parts is reached at the temperature extremes. if the reference voltage is used to measure both voltage and current, t he identical errors of 0.252% add up to a maximum wh registration error of 0.504%. the maximum deviation of 630 ppm (or 0.0 63 %) for the 71m6513h is reached at the temperature extremes. if the reference voltage is used to measure both voltage and current, the identical error s of 0.0 63 % add up to a maximum wh registration error of 0.1 26 %. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 83 of 104 a maxim integrated products brand figure 31 : error band for vref over temperature (regular - accuracy parts) figure 32 : error band for vref over temperature (high - accuracy parts) crystal oscillator the oscillator drives a standard 32.768 khz watch crystal. the osci llator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability . the oscillator power dissipation is very low to maximize the lifetime of any battery backup device attac hed to vbat. board layouts with minimum capacitance from xin to xout will require less battery current. good layouts will have xin and xout shielded from each other. - 2800 - 2400 - 2000 - 1600 - 1200 - 800 - 400 0 400 800 1200 1600 2000 2400 2800 - 40 - 20 0 20 40 60 80 error band (ppm) over temperature ( c) 40 ppm/ c 40 ppm/ c - 1000 - 800 - 600 - 400 - 200 0 200 400 600 800 1000 - 40 - 20 0 20 40 60 80 error band (ppm) over temperature ( c) - 10 ppm/ c +10 ppm/ c downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 84 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand for best rejection of electromagnetic interference, connect the crystal body and the ground t erminals of the two crystal capacitors to gndd through a ferrite bead. no external resistor should be conne cted across the crystal, since the oscillator is self - biasing. connecting l cds the 71m6513 has a lcd controller on - chip capable of controlling static or multiplexed lcds. figure 33 shows the basic connection for a lcd. figure 33 : connecting lcds figure 34 shows how 5v lcds can be operated even when a 5v supply is not available. setting the i/o ram re gister lcd_bsten to 1 starts the on - chip boost circuitry that will output an ac frequency on the vdrv pin. using a small cou pling capacitor, two general - purpose diodes and a reservoir capacitor, a 5vdc voltage is generated which can be fed back into the vlcd pin of the 71m6513. the lcd drivers are enabled with the i/o register lcd_on ; i/o register lcd_fs is used to adjust contrast, and lcd_mode selects the operation mode (lcd type). segments 71m6513 lcd commons segments 71m6513 lcd commons downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 85 of 104 a maxim integrated products brand figure 34 : lcd boost circuit connecting i2c eeproms i2c eeproms or other i2c compatible devices should be connected to the dio pins dio4 and dio 5, as shown in figure 35 . pull - up resistors of roughly 3k ? to v3p3 should be used for both scl and sda signals. the dio_eex register in i/o ram must be set to 1 in order to convert the dio pins dio4 and dio5 to i2c pins scl and sda. figure 35 : eeprom connection connecting 5v devices in general, all pins of the 71m6513 are compatible with external 5v de vices. the exceptions are the power supply pins and the rx pin of the uart (see section electrical specifications). lcd_bsten segments 71m6513 5v lcd commons vlcd v3p3 5vdc vdrv v3p3 lcd_fs lcd_en lcd_mode contrast on/off lcd type lcd_bsten segments 71m6513 5v lcd commons vlcd v3p3 5vdc vdrv v3p3 lcd_fs lcd_en lcd_mode contrast on/off lcd type dio4 dio5 71m6513 eeprom scl sda v3p3 3k 3k dio4 dio5 71m6513 eeprom scl sda v3p3 3k 3k downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 86 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand figure 36 : interfacing rx to a 0 - 5v signal figure 36 shows how a 5v signal from an external device can be safely interf aced to the rx pin. 71m651x v in rx r1 = 100k ? v3p3 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 87 of 104 a maxim integrated products brand optical interface the pins opt_tx and opt_rx can be used for a regular serial interface, e.g. by connecti ng a rs_232 transceiver, or they can be used to directly operate optical components, e.g. an infrared diode and phototransistor implementing a flag interface. figure 37 shows the basic connections. the opt_tx pin becomes active when the i/o ram register opt_txdis is set to 0. figure 37 : connection for optical components connecting v1 and reset pins a voltage divider should be used to establish that v1 is in a safe range when the meter is in mission mode (v1 must be lower than 2.9v in all cases in order to keep the hardware watchdog timer enabled). for proper debugging or load ing code into the 71m6513 mounted on a pcb, it is necessary to have a provision like the head er shown above r1 in figure 38 . a shorting jumper on this header pulls v1 up to v3p3 disabling the hardware watchdog time r. figure 38 : voltage divider for v1 even though a functional meter will not necessarily need a reset swi tch, it is useful to have a reset pushbutton for pro totyping. when a circuit is used in an emi environment, the resetz pin should be supported by the external components shown in figure 39 . r 1 should be in the range of 200 ? , r 2 should be around 10 ? . the capacitor c 1 should be 1nf. r1 and c1 should be mounted as close as possible to the ic. in cases where the tra ce from the pushbutton switch to the restz pin poses a problem, r 2 can be removed. opt_tx r 2 r 1 opt_rx 71m6513 v3p3sys phototransistor led 100k 100pf v3p3sys opt_tx r 2 r 1 opt_rx 71m6513 v3p3sys phototransistor led 100k 100pf v3p3sys v in r 2 v1 r 1 r 3 10k v in r 2 v1 r 1 r 3 10k downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 88 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand figure 39 : external components for resetz connecting the v3 pin the following should be noted when connecting the v3 pin: 1) if t he v3 pin is unused it should be left floating or terminated to the vref pin . 2) if t he v3 pin is used as a comparat or input the digital input voltage applied to v3 should be limited to vbias 0.9v . 3) if t he v3 pin is used either as an auxiliary analog input, and temperature measurements are made and evaluated using the alternate multiplexer cycle , the v3 input voltage range mu s t be re stricted to vbias 0.9 v (i.e. 0.6 v to 2.4 v). otherwise, the temp or v3 measurement could be inaccurate. this precaution is particularly important for customers who are using the temp samples for temperature compensat ion, especially with the 71m6513 h devices. connecting a battery many meter manufacturers assemble the meter pcb with the 71m6513 ic and the othe r electronic components first and then join the meter pcb with the meter enclosure, sensors and other m ain components separately at a later production step. typically, programming, final test (ate), and calibration are performed after this second step. the following production sequence is strongly recommended: 1) during pcb assembly, when adding/inserting the battery, the board supply voltage (v3p3a, v3p3d) should be active (i.e. at 3.3 vdc), which can be achieved by briefly connecting t he battery to v3p3a/v3p3d through a jumper wire. after the battery is inserted with the board power active, the jumper wire should be removed. 2) the battery should then remain connected through factory test (a te), time on the shelf and shipment. in cases where it is not feasible to power v3p3a/v3p3d while inser ting the battery, it is recommended to isolate the battery in its holder using a removable piece of kapton tape or other isolating material. this i solation should then be removed once the meter is fully powered durin g the calibration and test process. r 1 resetz 71m6513 dgnd v3p3 r 2 v3p3 pushbutton c 1 200 1nf 10 r 1 resetz 71m6513 dgnd v3p3 r 2 v3p3 pushbutton c 1 200 1nf 10 downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 89 of 104 a maxim integrated products brand flash programming operational or test code can be programmed into the flash memory using either an in - circuit emulator or the flash download board module (fdbm) available from teridian . the flash programming procedure uses the e_rts, e_rxtx, and e_tclk pins. mpu firmware library all application - specific mpu functions mentioned above under application information are availabl e from teridian as a standard ansi c library and as ansi c source code. the code is ava ilable as part of the demonstration kit for the 71m6513 and 71m6513h ics. the demonstration kits come with the 71m6513 or 71m6513h ic pr eprogrammed with demo firmware mounted on a functional sample meter pcb (demo board). the demo board s allow for quick and eff icient evaluation of the ic without having to write firmware or having to supply an in - circuit emulator (ice). a reference guide for firmware development on the 71m6513 and 71m6513h is available as a separ ate do cument (software users guide, sug). the u sers manuals supplied with the demo kits contain mpu address maps for the demo code as well as other useful information, such as sample calibration procedures. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 90 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand specifications electrical specifications absolute maximum ratings supplies and ground pins: v3p3d, v3p3a ? 0.5v to 4.6v | v3p3d - v3p3a | 0v to 0.5v vlcd - 0.5v to 7v vbat - 0.5v to 4.6v gndd - 0.5v to +0.5v analog output pins: vref, vbias - 1ma to 1ma, - 0.5 to v3p3a+0.5v v2p5 - 1ma to 1ma, - 0.5v to 3.0v analog input pins: ia, va, ib, vb, ic, vc, v2, v3 - 0.5v to v3p3a+0.5v xin, xout - 0.5v to 3.0v rx - 0.5v to 3.6v opt_rx - 1ma to 1ma - 0.5 to v3p3a+0.5v digital input pins: dio0 - 21, e_rxtx, e_rst, e_isync/brkrq - 0.5 to 6v test, resetz - 0.5 to v3p3d+0.5v all other pins: input pins - 5ma to 5ma - 0.5v to v3p3d+0.5v output pins - 30ma to 30ma - 0.5 to v3p3d+0.5v temperature: operating junction temperature (peak, 100ms) 140 c operating junction temperature (continuous) 125 c storage temperature ? 45 c to 165 c solder temperature C 10 second duration 250 c esd stress: pins ia, va, ib, vb, ic, vc, rx, tx, e_rst, e_tclk, e_rxtx, e_tbus[n] 4kv all other pins 2kv stresses beyond absolute maximum ratings may cause permanent damage to th e device. these are stress ratings only and functional operation at these or any other conditions beyond those indicated under recomm ended operating conditions is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. all v o ltages are with respect to gnda. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 91 of 104 a maxim integrated products brand recommended operating conditions parameter condition min typ max unit 3.3v supply voltage ( v3p3a, v3p3d ) ? normal operation 3.0 3.3 3.6 v battery backup 0 3.45 v vlcd 2.9 5.5 v vbat no battery externally connect to v3p3d battery backup 2.0 3.8 v operating temperature - 40 85 oc ? v3p3a and v3p3d should be shorted together on the circuit board. gnda and gndd should also be shorted on the circuit board. logic levels parameter condition min typ max unit digital high - level input voltage, v ih 2 v3p3d v digital low - level input voltage, v il ? 0.3 0.8 v digital high - level output voltage v oh i load = 1ma v3p3d C 0.4 v3p3d v i load = 15ma v3p3d - 0.6 1 v digital low - level output voltage v ol i load = 1ma 0 0.4 v i load = 15ma 0.8 1 v input pull - up current, i il resetz ................................ ....... other digital inputs vin=0v 10 10 -1 100 100 1 a a a input pull down current, i ih test other digital inputs vin=v3p3d 10 -1 100 1 a a 1 guaranteed by design ; not production tested. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 92 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand supply current parameter condition min typ max unit v3p3a + v3p3d + vlcd current normal operation, v3p3a=v3p3d = vlcd =3.3v ckmpu=614khz vbat=3.6v no flash memory write 6.4 9.5 ma v3p3a current 3.7 4.3 ma v3p3d current 2.5 4.8 ma vlcd current 0.2 0.4 ma vbat current - 300 300 na v3p3d current normal operation, v3p3a=v3p3d = vlcd =3.3v vbat=3.6v, no flash memory write ckmpu=1,228khz ckmpu=2,456khz ckmpu=4,912khz 2.9 3.6 5.1 ma ma ma v3p3a + v3p3d current power save/sleep mode v3p3a=v3p3d = vlcd =3.3v, ce, adc, e_tclk, vref dis - abled ckmpu=153.5khz ckmpu=38.4khz 6 4.9 7 ma ma v3p3d current, write flash normal operation as above, except write flash at ma xim um rate. 7 ma vbat current, vbat=3.6v battery backup, 25c v3p3a=v3p3d = vlcd =0v f osc = 32khz 85c 2 4 a 4 1 12 1 a 1 guaranteed by design ; not production tested . 2.5v voltage regulator unless otherwise specified, load = 5ma parameter condition min typ max unit voltage overhead v3p3 - v2p5 reduce v3p3 until v2p5 drops 200mv 440 mv pssr ? v2p5/ ? v3p3 resetz=1, iload=0 -3 +3 mv/v downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 93 of 104 a maxim integrated products brand vref, vbias unless otherwise specified, vref_dis =0 parameter condition min typ max unit vref output voltage, vnom(25) ta = 22oc 1.193 1.195 1.197 v vref chop step 40 mv vref output impedance vref_cal =1, i load = 10a, - 10a 2.5 k vnom definition a vnom(t) = vref(22) + (t C 22)tc1 + (t C 22) 2 tc2 v -- if trimbga and trimbgb available ( 6513h ) -- vref temperature coefficients tc1 (linear) tc2 (quadratic) trimbga , trimbgb , trimm [2:0]: see trimsel , trim registers x(33 - 0.28y) + 0.33y + 7.9 x(0.02 - 0.0002y) C 0.46 where x = 0.1trimbgb - 0.14(trimm[2:0]+0.5), 900 370000 _ 500 2 _ ? ? = bga trim nom temp y v/c v/c 2 vref(t) deviation from vnom(t) )40|,22 max(| 10 )( )( 6 ? ? t vnom t vnom t vref - 10 10 ppm/oc -- if trimbga and trimbgb not available ( 6513 ) -- vref temperature coefficients tc1 (linear) tc2 (quadratic) 7.0 - 0.341 v/oc v/c 2 vref(t) deviation from vnom(t) )40|,22 max(| 10 )( )( 6 ? ? t vnom t vnom t vref ta = - 40oc to +85oc - 40 1 +40 1 ppm/oc vref aging ta = 25oc 25 ppm/ year vbias output voltage ta = 25oc ta = - 40oc to 85oc (- 1%) (- 2%) 1 1.5 1.5 1 (+1%) (+2%) 1 v v vbias output impedance i load = 1ma, - 1ma 240 500 a this relationship describes the nominal behavior of vref at differe nt temperatures. 1 guaranteed by design ; not production tested . crystal oscillator crystal is disconnected. test load is series 200pf, 100k ? connected between dgnd and xout. parameter condition min typ max unit maximum output power to crystal 4 crystal connected 1 w xin to xout capacitance 1 3 pf capacitance to dgnd 1 xin xout 5 5 pf pf watchdog rtc_ok threshold 25 khz downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 94 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand adc converter, vdd referenced fir_len =0, vref_dis =0, vddrefz =0 parameter condition min typ max unit recommended input range (vin - v3p3a ) - 250 250 mv peak voltage to current crosstalk: ) cos( * 10 6 vcrosstalk vin vin vcrosstalk ? vin = 200mv peak, 65hz, on va, vb, or vc vcrosstalk = largest measurement on ia, ib, or ic - 10 1 10 1 v/v thd (first 10 harmonics) 250mv - peak 20mv - peak vin=65hz, 64kpts fft, blackman - harris window - 75 - 90 db db input impedance vin=65hz 40 90 k temperature coefficient of input impedance vin=65hz 1.7 /c lsb size fir_len =0 355 nv/lsb digital full scale + 884736 lsb adc gain error vs %power supply variation 3.3/ 3 3 100 / 357 10 6 a p v v nv nout in pk ? ? vin=200mv peak, 65hz v3p3a=3.0v, 3.6v 50 ppm/% input offset (vin - v3p3a ) - 10 10 mv 1 guaranteed by design ; not production tested . optical interface parameter condition min typ max unit opt_tx v oh ( v3p3d - opt_tx ) i source =1ma 0.4 v opt_tx v ol i sink =20ma 0.7 v opt_rx vin threshold (vin rising +vin falling )/2 200 250 300 mv opt_rx vin hysteresis (vin rising - vin falling ) 5 30 mv opt_rx input impedance |vin|300mv 1 m temperature sensor parameter condition min typ max unit nominal sensitivity (s n ) 2 t a =25oc, t a =75oc nominal relationship: n(t)= s n *t+n n - 900 lsb/oc nominal offset (n n ) 2 40000 0 lsb temperature error 1 n s n tn t err ))25( )(( )25 ( ? ? ? = t a = - 40oc to +85oc -3 1 3 1 oc 1 guaranteed by design ; not production tested . 2 this parameter defines a nominal relationship rather than a measur ed parameter. correct circuit operation is verified with other specs that use this nominal relationship as a reference. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 95 of 104 a maxim integrated products brand lcd boost parameter condition min typ max unit vdrv frequency osc/2 hz vdrv sink current vol=1.5v 1.2 2.75 ma vdrv source current voh=1.5v 1.2 2.6 ma vlcd target voltage 4.5 5.5 v vlcd input current vlcd=5.0v, lcd_fs =1f, lcd_mode =0,1,2,3 lcd_bsten =1 450 a lcd drivers applies to all com and seg pins. unless otherwise stated, vlcd= 5.0v, lcd_fs =1f parameter condition min typ max unit vlc0 max voltage ( lcd_fs =1f) with respect to vlcd - 0.2 0 v vlc0 min voltage ( lcd_fs =00) with respect to vlcd*0.7 - 0.2 0.2 v vlc1 voltage, 1/3 bias ? bias with respect to 2*vlcd/3 with respect to vlcd/2 - 10 - 10 +10 +10 % % vlc0 voltage, 1/3 bias ? bias with respect to vlcd/3 with respect to vlcd/2 - 15 - 10 +15 +10 % % output impedance ? i load =10a 30 k rtc parameter condition min typ max unit range for date 2000 - 2255 year resetz parameter condition min typ max unit reset pulse width 5 s reset pulse fall time 1 1 s 1 guaranteed by design ; not production tested . downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 96 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand comparators parameter condition min typ max unit offset voltage v1 - vbias v2 - vbias v3 - vbias - 20 - 20 - 20 15 15 15 mv mv mv hysteresis current v1 v2 v3 vin = vbias - 100mv 0.8 0.8 0.8 1.2 1.2 1.2 a a a response time v1 v2 v3 + 100mv overdrive 2 0.5 0.5 15 50 50 s s s wd disable threshold ( v1 - v3p3a ) - 400 - 10 mv ram and flash memory parameter condition min typ max unit ce ram wait states ckmpu = 4.9mhz 5 cycles ckmpu = 1.25mhz 2 cycles flash write cycles - 40c to +85c 20,000 cycles flash data retention 25c 100 years flash data retention 85c 10 years flash byte writes between page or mass erase operations 2 cycles flash memory timing parameter condition min typ max unit write time per byte 42 s page erase (512 bytes) 20 ms mass erase 200 ms eeprom interface parameter condition min typ max unit write clock frequency ckmpu=4.9mhz, using interrupts 78 khz ckmpu=4.9mhz, bit - banging dio4/5 150 khz downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 97 of 104 a maxim integrated products brand recommended external components name from to function value unit c1 v3p3a agnd bypass capacitor for 3.3v supply 0.1 20% f c2 v3p3d dgnd bypass capacitor for 3.3v supply 0.1 20% f xtal xin xout 32.768khz crystal. electrically similar to ecs ecx - 3ta series 32.768 khz cxs xin agnd load capacitor for crystal (depends on crystal specs and board parasitics). 22 10% pf cxl xout agnd 22 10% pf cv1 v1 agnd bypass capacitor for v1 0.1 20% f cbias vbias agnd bypass capacitor for vbias 1000 20% pf c bst 1 vdrv external boost charging capacitor 33 20% nf c bst 2 vlcd dgnd boost bypass capacitor 0.22 20% f c2p5 v2p5 dgnd bypass capacitor for v2p5 0.1 20% f rtst test dgnd resistor for test 10k ? 10% f downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 98 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand packaging information 100 - pin lqfp package outline (bottom view) 1 0.50(0.0197)typ. 0.05(0.002) 0.15(0.006) 0.18(0.007)0.27(0.011) 0.60(0.024) typ. 13.8(0.543) 14.2(0.559) 15.7(0.618)16.3(0.641) 15.7(0.618)16.3(0.641) 1.40(0.055)1.60(0.063) top view side view notes: controlling dimensions are in mm. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 99 of 104 a maxim integrated products brand pinout (top view) 1 23 4 5 6 7 8 9 1011 12 1314 15 1617 1819 2021 22 23 24 25 2627 28 29 30 31 32 3334 35 36 37 38 39 40 41 4243 44 45 4647 48 49 50 63 62 61 60 5958 57 5655 54 53 52 51 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 vbias e_tclkseg33/dio13 seg32/dio12 e_rst vlcd nc xouttest xin gndanc opt_rx v1 v2 v3 vrefia ib va vb vc v3p3a gnda ic gndd seg14 seg13 nc seg12 seg11 nc nc nc nc seg10 seg9 seg7/mux_sync seg8 nc seg6/srdy seg36/dio16 nc seg35/dio15 seg34/dio14 e_isync/brkrq seg2 seg1 seg15 seg0 gndd e_rxtx opt_tx tmuxout seg37/dio17 v3p3d dio_3 com1 com2 com3 tx seg3/sclk vdrv cktest com0 seg4/ssdata seg5/sfr e_tbus[3]e_tbus[2] dio_0 seg38/dio18 dio_1dio_2 e_tbus[0] e_tbus[1] seg27/dio7 seg39/dio19seg26/dio6 seg25/dio5 seg29/dio9 rxseg31/dio11 gnddresetz v2p5 vbat seg24/dio4 seg23seg22 seg28/dio8seg41/dio21 seg40/dio20 ncseg19 seg18 seg17 seg16 seg30/dio10 seg20 seg21 teridian 71m6513-igt/71m6513h-igt downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 100 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand pin descriptions power/ground pins name pin # type description gnda 76,91 p analog ground: this pin should be connected directly to the analog ground plane. gndd 1, 40, 75 p digital ground: this pin should be connected directly to the digital ground plane. v3p3a 77 p analog power supply: a 3.3v analog power supply should be connected to this pin. v3p3d 9 p digital power supply: a 3.3v digital power supply should be connecte d to this pin. vbat 72 p battery backup power supply. a battery or super - capacitor is to be connected between vbat and gndd. if no battery is used, connect vbat to v3p3d. v2p5 73 o output of the 2.5v regulator. a 0.1f capacitor to gnda should b e connected to this pin. vlcd 96 p lcd power supply. nc 32,33,36, 42,43,44, 47,55,90,95 -- no connect analog pins name pin # type circuit description ia ib ic 84 83 82 i 6 line current sense inputs: these pins are voltage inputs to the interna l a/d con - verter. typically, they are connected to the output of a current transformer. un used pins must be connected to v3p3a. va vb vc 80 79 78 i 6 line voltage sense inputs: these pins are voltage inputs to the inte rnal a/d con - verter. typically, they are connected to the output of a resist or divider. un used pins must be connected to v3p3a. v1 v2 v3 88 87 86 i 7 comparator inputs - voltage inputs to the internal comparator: the voltages applied to these pins are compared to vbias. if the volt age is above vbias, the corre - sponding comparator output will be high (1). the outputs are maintai ned in the comp_stat register. a typical application is to sense the voltage on the d c supply using an ex ternal resistor di vider to scale the power supply voltage to a level that triggers the comparator at the desired voltage drop. v1: this pin is part of the reset circuitry. it also controls t he hardware watchdog timer. a 0.1f capacitor to gnda should be connected to this pin. v2: compara tor input. if un used, this pin must be connected to v3p3a or ground. v3: comparator input , also available to the adc during alternative multiplexer cycles. if not used for measuring or sensing purposes, the v3 pin should e ither be left unconnected or be connected to the vref pin. see precautions on p age 88 . vbias 81 o 9 reference voltage used by the power fault detection circuit. a 1,000pf capacitor to gnd should be connected to this pin. vref 85 i/o 9 voltage reference for the adc. a 0.1f capacitor to gnda should be connected to this pin. xin, xout 92 94 i 8 crystal inputs: a 32khz style crystal should be connected across these pins. typically, a 2 2- 27 pf capacitor is also connected from each pin to gnda. see cryst al manufacturer datasheet for details. vdrv 7 o 4 voltage boost output. pin types: p = power, o = output, i = input, i/o = input/outp ut the circuit number denotes the equivalent circuit, as specified unde r i/o equivalent circuits. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 101 of 104 a maxim integrated products brand digital pins name pin # type circuit description dio_3, dio_2, dio_1, dio_0 21 20 19 18 i/o 3, 4 digital input/output pins 0 through 3. if un used, these dio pins must be configured as outputs or terminated to v3p3 or ground. com3, com2, com1, com0 25 24 23 22 o 5 lcd common outputs: these 4 pins provide the select signals for the lcd display. seg0seg2, seg8seg23 see pinout o 5 dedicated lcd segment output. seg24/dio4 . seg41/dio21 see pinout i/o 3, 4, 5 multi - use pins, configurable as either lcd seg driver or dio (dio4 = sck, dio5 = sda when configured as eeprom i/f, wpulse = dio6, varpulse = dio7 when configured as pulse outputs). if un used, these pins must be configured as outputs or terminated to v3p3 /ground. seg7/mux_sync 37 o 4, 5 multi - use - pin lcd segment output/ mux_sync is output for syn chron - ous serial interface seg6/srdy 35 i/o 2, 5 multi - use - pin, lcd segment outputs/ srdy input for synchronous serial interface. if un used, this pin must be terminated to ground. seg5/sfr 11 o 4, 5 multi - use - pin, lcd segment output/ sfr output for ssi. seg4/sdata 10 o 4, 5 multi - use - pin, lcd segment output/ sdata output for ssi. seg3/sclk 6 o 4, 5 multi - use - pin, lcd segment output/ sclk output for ssi. resetz 74 i 1 this pin is used to reset the chip into a known state. for normal operation, this pin is set to 1. to reset the chip, this pin is driven to 0. this pin has an internal 30a (nominal) current source pull - up but no schmitt - trigger circuitry. th e mini mum width of the pulse is 5s. a 0.1f capacitor to gnda should be connected to this pin. since the chip resets itself at power - up, no other external reset circuitry is required. rx 71 i 3 uart input. the voltage applied at this input must be below 3.6v. if un - used, the rx pin must be terminated to v3p3 or ground. tx 5 o 4 uart output. opt_rx 89 i 7 optical receive input: this pin receives a signal from an extern al photo - detector used in an ir serial interface. if un used, the opt_rx pin must be terminated to v3p3 or ground. opt_tx 3 o 4 optical led transmit output: this pin is designed to directly dr ive an led for transmitting data in an ir serial interface. can be tristated with opt_txdis to be multiplexed with other dio pins. cktest 8 o 4 clock pll output. can be enabled and disabled b y ckout_en . tmuxout 4 o 4 digital output test multiplexer. controlled by tmux [3:0]. e_rxtx 2 i/o 1, 4 emulator serial data. e_tbus[3] e_tbus[2] e_tbus[1] e_tbus[0] 12 13 14 15 o 4 emulator trace bus. these pins have internal pull - up resistors. e_isync/brkrq 29 i/o 1, 4 emulator handshake. this pin has an internal pull - up resistor. e_tclk 100 o 4 emulator clock. this pin has an internal pull - up resistor. e_rst 97 i/o 1, 4 emulator reset. this pin has an internal pull - up resistor. test 93 i 7 for teridian internal use. must be connected to gndd via a 10k ? resistor. pin types: p = power, o = output, i = input, i/o = input/outp ut the circuit number denotes the equivalent circuit, as specified unde r i/o equivalent circuits. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 102 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand i/o equivalent circ uits: oscillator equivalent circuit type 8: oscillator i/o digital input equivalent circuit type 1: standard digital input or pin configured as dio input with internal pull-up gndd 110k v3p3d cmos input v3p3d digital input pin digital input type 2: pin configured as dio input with internal pull-down gndd 110k gndd cmos input v3p3d digital input pin digital input type 3: standard digital input or pin configured as dio input gndd cmos input v3p3d digital input pin cmos output gndd v3p3d gndd v3p3d digital output equivalent circuit type 4: standard digital output or pin configured as dio output digital output pin lcd output equivalent circuit type 5: lcd seg or pin configured as lcd seg lcd driver gndd lcd seg output pin to mux gnda v3p3a analog input equivalent circuit type 6 : adc input analog input pin comparator input equivalent circuit type 7: comparator input gnda v3p3a to comparator comparator input pin to oscillator gndd v3p3d oscillator pin vref equivalent circuit type 9: vref from internal reference gnda v3p3a vref pin v2p5 equivalent circuit type 10: v2p5 from internal reference gndd v3p3d v2p5 pin vlcd equivalent circuit type 11: vlcd power gndd lcd drivers vlcd pin vbat equivalent circuit type 12: vbat power gndd power down circuits vbat pin downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet s eptember 201 1 ? 2005 - 2011 teridian semiconductor corporation page: 103 of 104 a maxim integrated products brand ordering information part description ordering number package marking 71m6513 100 - pin lead - free lqfp, 0.5% accuracy 71m6513 - igt/f 71m6513 - igt 71m6513 100 - pin lead - free lqfp, 0.5% accuracy, t&r 71m6513 - igt r /f 71m6513 - igt 71m6513h 100 -p in lead - free lqfp, 0.1% accuracy 71m6513h - igt/f 71m6513h - igt 71m6513h 100 - pin le ad - free lqfp, 0.1% accuracy, t&r 71m6513h - igtr/f 71m6513h - igt revision history revision date description 2.0 11/23/2005 initial release 2.1 11/30/2005 updated electrical specification (tc1/tc2, fuse descriptions) 2.2 4/17/2006 improved mpu register (sfr) description. added information in electrical specification s (adc resolution 355nv/lsb with fir_len =0, formula for temperature coefficients, 38 khz mpu clock, vref aging information , current consumption in low - power mode , r emoved note on adc count [ 3.589,461 * 600 * 7.8e - 9 = 169v ] ). improved ce description ( a dded x to pulse rate formula , temp_nom default value, apulser and apulsew update by mpu, relation between adc cycles and mux_div . added notes and clarifications on flash write operations. added information in applications section on connection of v3, crystal frequency variations and frequency measurement. improved figures 4 and 5. added caution note s for timing required for sw wdt and for conditions blocking interrupt processing. added note in pin descriptions on connection of v3. 2.3 3/14/2007 added i/o equivalent circuits and interrupt structure diagram . added note in ce section stating that ce status word must be read right after the ce_busy interrupt. deleted flsh_tmr from list of pins in logic levels. upda ted table 51 (dio pins) and figure 11. changed capacitor value for xin/xout in pin descriptions and in recommended external components. added items in electric al specification ( temperature range for maximum write cycles, flash retention time for +85c, maximum number of writes in between flas h erase operations ) . added note in pin descriptions on exte rnal reset circuitry . added cautionary notes for eck_dis and se cure bits. added re quirements for termination in pin tables for dio_0 - dio_3, dio/seg, rx, opt_rx pins. added explanation of srdy polarity. downloaded from: http:///
71m6513/71m6513h 3- phase energy meter ic data sheet august 201 1 page: 104 of 104 ? 2005 - 2011 teridian semiconductor corporation a maxim integrated products brand revision history (continued) revision date description 2.4 8/17/2007 removed all reference s to rom versions . removed reference to 3 rd uart in hardware overview using bit - bang technique. added note stating that bit - banging of dio4/5 is discouraged. added a 1,000pf capacitor to gnd should be connected to this pin for vbias in analog pin descriptions. a dded precaution regarding i/o ram locations affected by flash write under flash mem ory. added remark in mpu/ce communication on inaccuracy of accumulation interval as compared to rtc. modified ce interface de scription. changed in electrical spe - cification s: tc1 to +7.0 ( vref section ), recommended capacitor values for xin/xout and crystal type. corrected diagram for rogowski coil (figure 30). fixed table 56. 2.5 8/12/2008 updated package information from iel (exposed pad lqfp) to igt/f package type (title page, package drawing, and ordering in forma tion). updated teridian street address in formation. updated explanation for v3sqsum re gister in ce interface description. added revision history table to replace separate revision notes. 2.6 12 /10 changed information on wh accuracy on title page. added section on delay compensation in ce description. corrected uart description in mpu section. added cautionary note in ce program and environment section stating that operating ce code with env ironmental settings other than those specified in the data sheet will lead to unpredictable results. deleted graphs showi ng typical performance over temperature. added crystal oscillator informati on in application information section. added note in applications section stating that high source impedance sensor circuits should be avoided. clarified guaranteed by design and tested in production information in electrical specifications section. changed font for all sfr and i/o ram register variables to tim es new roman italic. corrected various typos. 3 9/11 added the following: - changed 50ppm/ c to 40ppm/ c (page 1). - e xplanation of scaling factors applied to ppmc and ppmc2 ( page 7 3). - explanation of error bands for temperature compensation ( page 82 ). - precautionary notes regarding the voltage range of the v3 pin (page 88 ). - precautionary notes for connecting a battery (page 88 ). downloaded from: http:///

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